 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL |
| What is claimed is: 1. A SONOS flash memory device, comprising: a SONOS flash memory cell; and at ... |
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| Temperature responsive valve assembly for a pneumatic spring |
| The gas spring assembly according to the present invention provides a temperature responsive valve ... |
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| Method for fabricating resistors within semiconductor integrated circuit devices |
| In accordance with a preferred embodiment of the present invention, a resistor is fabricated by ... |
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| Power injector apparatus |
| As mentioned above, the main object of the present invention is to provide a power injector ... |
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| Integrated circuit having a void between adjacent conductive lines |
| The invention overcomes the disadvantages and difficulties of the prior art by introducing new ... |
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| Non-volatile memory utilizing a thin film, floating gate, amorphous transistor |
| What is claimed is: 1. A non-volatile memory comprising: data storing means comprising an amorphous,... |
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Acoustic wave device and process for forming the same
| Details |
Inventors: Finder, Jeffrey M.; Eisenbeiser, Kurt; Ramdani, Jamal; Droopad, Ravindranath; Ooms, William Jay;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Budd; Mark O.
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
High quality epitaxial layers of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. |
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DETAILED DESCRIPTION OF THE DRAWINGS FIG.
1 illustrates schematically, in cross section, a portion of a microelectronic structure 20 in accordance with an embodiment of the invention.
Microelectronic structure 20 includes a monocrystalline substrate 22, an accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of piezoelectric material, which is preferably monocrystalline.
In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry.
The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
Structure 20 may also include a template layer 30 between the accommodating buffer layer and piezoelectric material layer 26.
As will be explained more fully below, the template layer helps to initiate the growth of the piezoelectric material layer on the accommodating buffer layer.
The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and, by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter.
The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA.
Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
Substrate 22 can also be of a compound semiconductor material
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Active Solid-state 
