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| Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides |
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| UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL |
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| Temperature responsive valve assembly for a pneumatic spring |
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| Method for fabricating resistors within semiconductor integrated circuit devices |
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| Power injector apparatus |
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Capacitor constructions, DRAM constructions, and semiconductive material assemblies
| Details |
Inventors: Moore, John T.; Blalock, Guy T.; DeBoer, Scott Jeffrey;
Assignee: Micron Technology, Inc. (Boise, ID)
Primary Examiner: Nguyen; Tuan H.
Assistant Examiner:
Attorney, Agent or Firm: Wells St. John P.S.
In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching the second material at a faster rate than the first material. In another aspect, the invention includes a capacitor forming method, comprising: a) forming a wordline over a substrate; b) defining a node proximate the wordline; c) forming an etch stop layer over the wordline, the etch stop layer comprising carbon; d) forming an insulative layer over the etch stop layer; e) etching through the insulative layer to the etch stop layer to form an opening through the insulative layer; and e) forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening. In yet another aspect, the invention includes a semiconductive material assembly, comprising: a) a semiconductive substrate; and b) a layer over the semiconductive substrate, the layer comprising silicon, nitrogen and carbon. |
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DETAILED DESCRIPTION In one aspect, the invention encompasses an etching process.
A first material is provided over a substrate.
The first material comprises from about 2% to about 20% carbon (by weight).
A second material is provided over the first material.
The second material is etched at a faster rate than the first material.
In another aspect, the invention encompasses a capacitor forming method.
A wordline is formed over a substrate and has a sidewall.
An insulative spacer is formed along the sidewall.
A node is defined proximate the wordline.
An etch stop layer is formed over the wordline and over the insulative spacer.
At least one of the etch stop layer and the insulative spacer comprises carbon.
An insulative layer is formed over the etch stop layer.
The insulative layer is etched to form an opening through the insulative layer and to the etch stop layer.
A capacitor construction is formed.
The capacitor construction comprises a storage node, dielectric layer and a second electrode.
At least a portion of the capacitor construction is within the opening.
In yet another aspect, the invention encompasses a DRAM forming method.
A pair of wordlines are formed over a substrate.
Three nodes are defined proximate the wordlines.
The three nodes comprise a first node, second node and third node.
The second node is in gated electrical connection with the first node through one of the wordlines and in gated electrical connection with the third node through the other of the wordlines.
An etch stop is formed proximate the wordlines.
The etch stop comprises carbon.
An insulative layer is formed over the etch stop.
A first, second and third opening are formed to extend through the insulative layer.
The forming the first second and third openings comprises etching through the insulative layer to the etch stop.
A first capacitor construction is formed in electrical connection with the first node, a second capacitor construction is formed in electrical connection with the third node, and a bit line contact is formed in electrical connection with the second node
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