Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

DETAILED DESCRIPTION The above mentioned problems with memory cells and other problems are addressed by the present invention and which will be understood by reading and studying the following specification.
A memory cell is described which includes a vertical transistor with a trench plate trench capacitor and a body contact.
In particular, one embodiment of the present invention provides a memory cell.
The memory cell includes an access transistor.
The access transistor is formed in a pillar of single crystal semiconductor material.
The transistor has first and second source/drain regions and a body region that are vertically aligned.
The memory cell also includes a body contact that is coupled to the body region.
A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact.
A trench capacitor is also included.
The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.
An insulator layer separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.
In another embodiment, a memory device is provided.
The memory device includes an array of memory cells.
Each cell includes a vertical access transistor formed of a semiconductor pillar that extends outwardly from an insulator layer on a substrate.
The access transistor has body and first and second source/drain regions, a gate disposed adjacent to a side of the pillar adjacent to the body region, and a trench capacitor.
The first plate of the trench capacitor is integral with the first source/drain region and a second plate of the capacitor is disposed adjacent to the first plate.
A number of bit lines are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor so as to form columns of memory cells.
A number of word lines are also provided