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 Input circuit for protecting against damage caused by electrostatic discharge

Details
Inventors: Krieger, Gadi; Eitan, Boaz;
Assignee: WaferScale Integration, Inc. (Fremont, CA)
Primary Examiner: Edlow; Martin H.
Assistant Examiner: Featherstone; Donald J.
Attorney, Agent or Firm: Leeds; Kenneth E., MacPherson; Alan H., Winters; Paul J.

A circuit for protecting an input MOS FET (Q1) from electrostatic discharge pulses includes a plurality of diodes (D112a through D112f) coupled to the bonding pad (102) of an integrated circuit via a plurality of resistors (R110a through R110f). The resistors prevent excessive current from flowing through and hence damaging any of the diodes. The diodes possess a unique shape which maximizes the perimeter to surface area ratio and therefore permits more efficient energy dissipation along the periphery of the diodes. The diodes are adapted to break down in response to an excessive voltage at the bonding pad and therefor protect the gate structure of the input transistor. Also included in the circuit is a protective bipolar transistor (Q2) having a collector coupled to the bonding pad, an emitter coupled to ground and a base resistively coupled to ground. When a large voltage is applied to the bonding pad and the break down of the diodes is insufficient to limit the voltage at the bonding pad, the collector base junction of the bipolar transistor breaks down thus providing an added element of protection for the input MOS FET. The circuit of the present invention also includes a second resistor diode network which further attenuates the voltage presented to the gate of the input transistor.

DETAILED DESCRIPTION Referring to FIGS.
2 and 5, a circuit 100 constructed in accordance with the present invention protects the gate insulation (typically silicon dioxide) of an MOS transistor Q1 in an integrated circuit.
Circuit 100 is connected to a bonding pad 102 which is typically connected to an input pin (not shown) of the integrated circuit.
Pad 102 is connected to a metal lead 104 which in turn is connected to an N+ region 106 by a set of vias 108.
N+ region 106 is formed within an N- well 110.
N- well 110 includes a plurality of fingers 110a through 110f which are used to provide resistive electrical connection between N+ region 106 and a plurality of N+ regions 112a through 112f, respectively.
The resistance of fingers 110a through 110f are illustrated in the schematic diagram of FIG.
5 as resistors R110a through R110f, respectively.
N+ regions 112a through 112f form the cathodes of diodes D112a through D112f of FIG.
5, respectively.
When bonding pad 102 receives an electrostatic pulse and the voltage at bonding pad 102 increases, the voltage at lead 104 increases.
If the voltage at lead 104 rises above the breakdown voltage of diodes D112a through D112f, these diodes break down and current is permitted to flow from lead 104 through diodes D112a through D112f and to ground.
By providing a current path between lead 104 and ground when lead 104 receives an ESD pulse, circuit 100 decreases the likelihood that the pulse will damage input transistor Q1 by reducing the voltage that would otherwise be present at the gate of transistor Q1.
One feature of the present invention is the provision of resistors R110a through R110f between lead 104 and the cathodes of diodes D112a through D112f, respectively.
These resistors prevent.
excessive current from destroying diodes D112a through D112f.
It would normally be possible for one of the diodes D112a through D112f to conduct more current than the others.
For example, it is known that if there is a defect in the crystal structure of a diode, more current tends to flow in the vicinity of the defect, with a resulting increase of energy dissipation at that point



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