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 Integrated circuit having a void between adjacent conductive lines

Details
Inventors: Reinberg, Alan R.;
Assignee: Micron Technology, Inc. (Boise, ID)
Primary Examiner: Ngo ; Ngan V.
Assistant Examiner:
Attorney, Agent or Firm: Fletcher, Yoder & Edwards

The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier form a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

DETAILED DESCRIPTION The invention overcomes the disadvantages and difficulties of the prior art by introducing new methods and devices wherein the area between closely spaced conductors exhibits a dielectric constant approaching 1.
To that end, the present invention proposes several methods for leaving a void between closely spaced conductors (usually metal lines) in a semiconductor device.
In conjunction with these methods, the invention also proposes a semiconductor device wherein there is a void between closely spaced conductors (metal lines).
One method of the current invention calls for creating a barrier above closely spaced conductors (typically metal lines) by using a low-melting-point glass or organic material.
More specifically, after depositing the conductors, this method calls for depositing a layer of low-melting-point glass or organic material.
Both the glass and the conductor are then etched using a mask and photoresist process.
Furthermore, after removal of the photoresist, the wafer is subjected to a heat cycle.
The heat cycle is properly adjusted to cause the glass to sag laterally.
Where conductors are closely spaced, the sagging glass from adjacent lines will touch or otherwise form a barrier to subsequently applied layers.
The result is a semiconductor product wherein a void exists between the closely spaced conductors.
Another method of the current invention creates a barrier between closely spaced conductors by using sidewall film.
In this method, a conductive layer is deposited and then etched using a mask and photoresist process.
The wafer is then subjected to a heat cycle before the photoresist is removed.
The heat cycle is properly adjusted to cause the photoresist to sag laterally.
Where conductors are closely spaced, the sagging photoresist from adjacent lines with touch or near-touch.
The sagging photo resist carries the sidewall film on its formerly vertical edge.
Therefore, being carried by the sagging photoresist, the sidewall film from closely spaced conductors will arc together or near together forming a barrier to subsequently applied layers



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