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Layout pattern for improved MOS device matching
| Details |
Inventors: Wong, Shyh-Chyi; Tseng, Pin-Nan; Ting, Jyh-Kang;
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu, TW)
Primary Examiner: Martin-Wallace; Valencia
Assistant Examiner: Eckert, II; George C.
Attorney, Agent or Firm: Saile; George O., Ackerman; Stephen B., Prescott; Larry J.
This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics. |
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DETAILED DESCRIPTION What is claimed is: 1.
A circuit layout, comprising: four or more metal oxide semiconductor field effect transistors each said transistor having a rectangular channel diffusion area bounded by a top edge, a bottom edge, an inside edge, and an outside edge wherein each said channel diffusion area has about the same length and about the same width and said transistors are arranged in a row so that said inside edge of each channel diffusion area is parallel to said inside edges of the remaining said channel diffusion areas, said outside edge of each channel diffusion area is parallel to said outside edges of the remaining said channel diffusion areas, said inside edge of each said channel diffusion area is parallel to said outside edge of each said channel diffusion area, said top edge of each said channel diffusion area is parallel to said bottom edge of each said channel diffusion area, said top edges of each said channel diffusion area lie on a single line, and said bottom edges of each said channel diffusion area lie on a single line; a number of gate electrodes equal to the number of said transistors wherein one of each said gate electrodes crosses each said channel diffusion area so that the edges of said gate electrodes are parallel to said top edge of said channel diffusion area; a source contact for each of said transistors; a drain contact for each of said transistors; a number of matched pairs of said transistors, wherein said inside edge of said channel diffusion area of each transistor in each said matched pair of transistors is adjacent to said channel diffusion area of another of said number of metal oxide semiconductor field effect transistors and said outside edge of said channel diffusion area of each transistor in each said matched pair of transistors is adjacent to said channel diffusion area of another of said number of metal oxide semiconductor field effect transistors; and electrode connections to interconnect said transistors.
2.
The circuit layout of claim 1 wherein each said transistors forming one said matched pair of transistors is adjacent to the other said transistor forming said matched pair of transistors
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Active Solid-state 
