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Logic cell having efficient optical proximity effect correction
| Details |
Inventors: Yamaguchi, Akira;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Hardy; David B.
Assistant Examiner:
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
There are provided a semiconductor device, basic cell library, a method for manufacturing a semiconductor device, and a method and mask for forming a basic cell library which can reduce the amount of poly-data to be corrected by the optical proximity effect correction (OPC), reduce the CAD processing time, perform correction by the OPC for each cell, and reduce the product turn around time. A basic cell registered in the basic cell library has a dummy wiring pattern previously formed on the peripheral portion thereof. With this structure, the distance between a polysilicon gate used in a circuit and the polysilicon wiring of an adjacent dummy wiring pattern in the basic cell can be determined in the cell. As a result, variations in the poly-widths of all of the polysilicon gates in the basic cell due to the optical proximity effect can be estimated, and therefore, a correction value by the OPC on a mask for correcting the gate width based on the variation in the poly-width can be determined in the cell. |
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DETAILED DESCRIPTION OF THE INVENTION There will now be described embodiments of this invention with reference to the accompanying drawings.
First, a first embodiment of this invention is explained with reference to FIGS.
7A, 7B, 7C and FIG.
8 which are plan views showing basic cells registered in the basic cell library of this invention.
In the basic cell library, basic cells used for constructing a semiconductor integrated circuit are registered, and at the time of manufacturing a semiconductor device, the basic cells registered in the basic cell library are adequately selected to make a layout design for forming a logic circuit.
The basic cells of this invention shown in the above drawing are used for laying out a standard cell type semiconductor device.
The basic cell has a layout structure for realizing a plurality of basic gates on a substrate and is constructed by an internal wiring such as a gate, diffusion regions and a dummy wiring pattern which is the important factor of this invention.
The basic cell includes an inverter, 2-input NAND, flip-flop, EX-OR, AND, NOR and is a layout structure for realizing a basic gate on the semiconductor substrate.
FIG.
7A shows an A cell registered in the basic cell library.
A dummy wiring pattern 4 of a polysilicon wiring pattern is formed along the cell frame which defines a cell region.
That is, the cell region is surrounded by the dummy wiring pattern 4.
In the cell region, one pair of diffusion regions (SDG) 2 used as source/drain regions are formed.
The diffusion regions 2 include a p+ diffusion region 21 and n+ diffusion region 22 and one polysilicon gate 3 is formed to extend over the diffusion regions 21, 22.
In this embodiment, the gate width w1 of the polysilicon gate 3 and the pattern width w2 of the dummy wiring pattern 4 are both set to 0.
3 .
mu.
m, for example.
The dummy wiring pattern 4 is formed of portions 41 which are parallel to the polysilicon gate 3 and portions 42 which are perpendicular to the polysilicon gate 3.
The parallel portion 41 causes a variation in the gate width due to the optical proximity effect in the polysilicon gate 3, but since the distance dO between the polysilicon gate 3 and the dummy wiring pattern 4 is constant, correction can be previously made in the state of basic cell if a variation in the gate width occurs in the polysilicon gate 3
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Active Solid-state 
