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 Method for producing a fully walled emitter-base structure in a bipolar transistor

Details
Inventors: Hebert, Francois;
Assignee: Avantek, Inc. (Milpitas, CA)
Primary Examiner: Chaudhuri; Olik
Assistant Examiner: Pham; Long
Attorney, Agent or Firm:

A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices. The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance. The peripheral emitter-base capacitance is substantially decreased by the oxide walls which surround the emitter sides. Since the sides of the emitter are walled, no lateral current injection can occur. Bipolar transistors which employ the claimed process exhibit an increased emitter-base breakdown and a reduced forward tunneling current since high sidewall doping levels are eliminated.

DETAILED DESCRIPTION An object of the present invention is to provide a process for producing a bipolar transistor structure which is self-aligned, employing a metal contacted monocrystalline silicon emitter region with a fully walled outer side surface, without using any polycrystalline or amorphous silicon.
Another object of the invention is to provide a process for producing a fully walled emitter-base structure having a metal silicide over the extrinsic base region and optionally a separately optimized metal silicide over the emitter region.
The claimed process allows production of a bipolar transistor structure having reduced parasitic capacitance, reduced emitter resistance, reduced lateral current injection, improved breakdown characteristics, and a low resistance extrinsic base region.
The claimed process is initiated by first providing a base island region on a semiconductor device having an epitaxial monocrystalline silicon layer under thin silicon oxide and silicon nitride layers.
A base dopant is introduced into the monocrystalline silicon layer before or after the thin silicon oxide and silicon nitride layers are formed.
An emitter region is defined by lithographically patterning a photoresist mask on top of the oxide and nitride layers.
The unmasked areas outside of the emitter region is referred to as the "extrinsic base region".
The extrinsic base region is directionally etched until all of the oxide and nitride layers and part of the silicon layer is removed, so that the etching depth of the silicon layer corresponds to the desired emitter/base junction depth.
The photoresist mask is removed leaving the oxide and nitride layers covering the emitter region.
Base dopant is introduced in the extrinsic base region.
A first oxide film is deposited over the base island region.
The first oxide film is directionally etched until an oxide sidewall is formed around the periphery of the emitter region.
A base dopant is introduced in the extrinsic base region which is not covered by the oxide sidewall



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