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Non-volatile memory utilizing a thin film, floating gate, amorphous transistor
| Details |
Inventors: Riggio, Jr., Salvatore R.;
Assignee: International Business Machines Incorporated (Armonk, NY)
Primary Examiner: Nelms; David C.
Assistant Examiner: Hoang; Huan
Attorney, Agent or Firm: Kashimba; Paul T., McKinley; Martin J., McKechnie; Doug
A memory controller generates control and address signal for accessing a non-volatile memory having a plurality of addressable cells. Each cell of the non-volatile memory includes a floating gate transistor (e.g., Q15) capable of storing charge (representing a binary 1 or 0) for extended, although not indefinite, periods of time. To refresh any charge that leaks off the floating gate, refresh circuitry (e.g., Q17-Q19) is provided to restore the charge on the gate to its original logical state. This refresh circuitry may be activated at "power-up." Each of the transistors in the memory are preferably thin film, amorphous silicon, "N" type transistors, including the floating gate transistor. |
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DETAILED DESCRIPTION What is claimed is: 1.
A non-volatile memory comprising: data storing means comprising an amorphous, thin film, floating gate transistor (FGT) having a data input for receiving a data bit to be stored in said transistor and a load transistor coupled to said FGT, said load transistor being operative to produce a data output signal representing the bit stored in said FGT; means for refreshing data stored in said data storing means; said data output signal is inverted relative to the bit inputted into said FGT; and said means for refreshing comprises an inverter for producing a feedback signal inverted relative to said data output signal, and selectively operated means for coupling said feedback signal into said data input of said FGT to refresh the data bit stored therein.
2.
The non-volatile memory of claim 1, wherein said inverter includes a plurality of amorphous, thin film transistors.
3.
The non-volatile memory of claim 2, wherein said floating gate transistor and said plurality of amorphous, thin film transistors are all of the same type, N or P.
4.
A non-volatile memory comprising: a plurality of memory cells; each memory cell comprising a thin film amorphous floating gate transistor (FGT) having a control gate; a source; a drain; a channel extending between said source and said drain; an insulator between said control gate and said source, said drain, and said channel; and a floating gate embedded in said insulator; selectively operated input means coupled to said control gate for writing a data bit into said FGT; selectively operated output means coupled to said FGT for reading said data bit from said FGT; and selectively operated refreshing means for refreshing said data bit stored in said FGT; said output means comprising a second transistor connected as a load device for limiting current flow through said FGT and producing a logic signal representing an output bit and an analog switch coupled to transmit said output bit out of said cell.
5.
The non-volatile memory in accordance with claim 4 wherein said refreshing means is operative to produce a refreshing signal of the same polarity as said data bit that was written into said FGT, said refreshing means further comprising a selectively actuated second analog switch for coupling said refreshing signal with said input means and said control gate to refresh the data bit stored in said FGT
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Active Solid-state 
