Nonvolatile memory device

DETAILED DESCRIPTION Accordingly, it is an object of the present invention to provide a programmable nonvolatile logic switch memory (register) device using a nonvolatile resistance memory device.
In an embodiment, there is provided a nonvolatile memory device comprising a write/read controller, a nonvolatile resistive memory device and a logic switch.
The write/read controller selectively controls write/read control signals enabled in a write mode.
As used herein, a nonvolatile resistive memory device is a circuit element that stores different logic values in the level of electrical resistance of one or more circuit elements, such that the states of resistance of the element or elements can be changed or set (e.
g.
, set to a high resistance or set to a low resistance) by controlling the amount of current that passes through the device when the write/read control signals are enabled.
The logic switch selects switching states depending on the different logic values pre-stored in the nonvolatile resistive memory device when the write/read control signals are disabled.
In an embodiment, there is also provided a nonvolatile memory device comprising a flip-flop unit, a nonvolatile resistive memory device, an access controller and a current supply unit.
The flip-flop unit includes a PMOS latch and a NMOS latch, and latch the opposite data.
The nonvolatile resistive memory device, which is connected between the PMOS latch and the NMOS latch, stores different logic values depending on states of resistance changed by the amount of current.
The access controller controls connection of a bitline and the flip-flop unit depending on an enable state of a wordline.
The current supply unit supplies current for changing data stored in the resistive memory device when the write/read control signals are enabled.
In an embodiment, there is also provided a nonvolatile memory device comprising a flip-flop unit, a nonvolatile resistive memory device and an access controller.
The flip-flop unit includes a NMOS latch for latching opposite data