Ovonic unified memory device and magnetic random access memory device

DETAILED DESCRIPTION The present invention has been made in order to solve the above problem and it is accordingly an object of the present invention to provide a semiconductor memory device capable of achieving high integration.
A semiconductor memory device according to the present invention includes: a semiconductor substrate; a junction transistor formed on the semiconductor substrate; an insulating layer which has a hole accepting at least part of the junction transistor and reaching a surface of the semiconductor substrate, and which is formed on the semiconductor substrate; and a storage element electrically connected to part of the junction transistor provided in the hole.
The storage element has a first state in which an electric resistance is relatively high and a second state in which an electric resistance is relatively low.
The junction transistor includes: a first conductive type well region formed in said semiconductor substrate; a second conductive type impurity region formed in the first conductive type well region so as to face to the hole; and a first conductive type conductive region provided in the hole so as to be in contact with the second conductive type impurity region.
In the semiconductor memory device, with such a structure, according to the present invention, the junction transistor is connected to the storage element.
Therefore, an electrical signal can be sent to the storage element at higher speed compared with a case where a field effect transistor or a diode is connected to the storage element.
Furthermore, since at least part of the junction transistor is provided in the hole, an area occupied by the junction transistor on the semiconductor substrate decreases, thereby enabling higher integration.
Preferably, the first state includes an amorphous state and the second state includes a crystalline state.
The first state includes an amorphous state and the second state includes a crystalline state.
The semiconductor memory device further includes a first heating layer which is provided in the hole so as to interpose between the storage element and the first conductive type conductive region to have an electric resistance higher than that of the first conductive type conductive region, and which heats the storage element