Semiconductor integrated circuit device having dummy pattern effective against micro loading effect

DETAILED DESCRIPTION It is therefore an important object of the present invention to provide a semiconductor integrated circuit device a dummy pattern of which makes a micro loading effect equivalent between a test pattern and a major pattern of an integrated circuit.
The present inventor contemplated the micro loading effect.
The present inventor noticed that the dummy gate electrodes 3a to 3f are surrounded by a wide vacant area 5 and that a major pattern in the major area was surrounded by other circuit components.
The present inventor concluded that the wide vacant area 5 suppressed the micro loading effect, because the reaction product easily escapes from the vicinity of the dummy gate electrodes 3a to 3f to the wide vacant area.
To accomplish the object, the present invention proposes to surround a central dummy pattern with a peripheral dummy pattern.
In accordance with the present invention, there is provided a semiconductor integrated circuit device fabricated on a semiconductor substrate having a major area and a test pattern area, comprising: a) an integrated circuit formed in the major area, and having a plurality of circuit components and a second circuit component, a plurality of pattern components being incorporated in the plurality of circuit components at intervals, the second circuit component being spaced from the plurality of pattern components by a first distance; b) a test component having a test pattern and used for evaluating at least one of the plurality of circuit components; and c) a peripheral dummy pattern surrounding the test component and spaced from the test pattern by a second distance equal to the first distance, the peripheral dummy pattern and the test pattern being concurrently patterned together with the plurality of pattern components.
The semiconductor integrated circuit device may further comprise a plurality of dummy test components concurrently formed inside of the peripheral dummy pattern, and the test pattern and the dummy test components may be spaced at second intervals equal to the first intervals