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| Nonvolatile memory device |
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| Method of forming single crystalline magnesia spinel film |
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Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device
| Details |
Inventors: Hasegawa, Masatoshi; Miyaoka, Shuichi; Akasaki, Hiroshi; Katayama, Masahiro;
Assignee: Hitachi, Ltd. (Tokyo, JP); Hitachi ULSI Systems Co., Ltd. (Tokyo, JP)
Primary Examiner: Whitehead, Jr.; Carl
Assistant Examiner: Dolan; Jennifer M
Attorney, Agent or Firm: Reed Smith LLP, Fisher, Esq.; Stanley P., Marquez, Esq.; Juan Carlos A.
Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal. |
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DETAILED DESCRIPTION Prior to the invention, the present inventors studied the possibility of high-speed testing of the RAM under the condition in which a low-speed testing apparatus is used.
The technique of interest which was studied concerned a technique in which a portion of the internal timing control configuration of the memory is made shiftable from the configuration of responding to the normal level transition of a synchronization signal such as the RAS signal to the configuration of responding to the level transition in the opposite direction only during testing (i.
e.
, a shift of the edge trigger is effected), and in which, during testing, the internal circuit of the memory is operated by a synchronization signal with an apparently short pulse width in combination with a pulse-width setting function or a pulse-duty ratio changing mechanism in a testing apparatus.
In the case of a dynamic RAM whose operating speed is not very high such as 100 MHz or less, through the above-described studied technique, by using the aforementioned clock signal of about 30 MHz it becomes possible to conduct an evaluation of response characteristics of the internal circuit, i.
e.
, those equivalent to a case in which the circuit is operated at the aforementioned 100 MHz, by the above-described control of the duty of the clock signal in the testing apparatus.
That is, the evaluation of the high-speed operation of the RAM becomes possible.
According to this studied technique, however, the test of the dynamic RAMs for which even higher-speed operation is required becomes difficult.
For example, in the case of a high-speed operating DRAM whose operating frequency is increased to about 400 MHz or thereabouts, the duty of the clock signal supplied from the above-described testing apparatus must be made extremely small, and the pulse duty becomes destroyed in a signal transmission path leading from the testing apparatus to the memory circuit, thereby making it impossible to reliably make an evaluation equivalent to that of a case in which the circuit is operated at the aforementioned 400 MHz or thereabouts
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Active Solid-state 
