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 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST*** *** NO IMAGES AVAILABLE*** Semiconductor device and manufacturing method thereof

Details
Inventors: Sato, Tsutomu; Mizushima, Ichiro; Tsunashima, Yoshitaka;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Potter; Roy
Assistant Examiner:
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett and Dunner, L.L.P.

A deep trench is formed in a silicon substrate. The inner surface of the trench is next coated with a thin polycrystalline silicon film (liner film) so as not to close the trench. A silicon germanium film (node electrode) is then formed on the thin polycrystalline silicon film so as not to close the trench. Next, a heat treatment is performed on the silicon germanium film thereby to flow only the silicon germanium so that the trench is filled.

DETAILED DESCRIPTION OF THE INVENTION Explained first will be a problem of a conventional method shown in FIGS.
6A to 6D which has been found by the present inventors.
According to studies by the present inventors, it has been clarified that a poly-crystallized amorphous silicon film 87 and a thin polycrystalline silicon film 86 flow integrally in the heat treatment step shown in FIG.
6D and clearances 88.
sub.
1 to 88.
sub.
4 are formed as a result in the trench 83 as shown in FIG.
7.
Particularly, if the aspect ratio of the trench 83 is as high as 10 or more, it is difficult for the conventional method to bury the trench 83 with a silicon film without causing clearances 88.
sub.
1 to 88.
sub.
4.
The clearances 88.
sub.
1 to 88.
sub.
4 of this kind cause a problem of increase in resistance of the amorphous silicon film 87 (node resistance).
Further, the clearance 88.
sub.
1 formed at an upper portion of the trench 83 as shown in the figure acts to separate the upper portion of the amorphous silicon film 87 from the other portions.
Consequently, a voltage of a predetermined level cannot be applied to the entire amorphous silicon film 87.
In other words, the voltage of a predetermined level is applied to only a part of the amorphous silicon film 87.
A problem hence arises in that the clearance 88.
sub.
1 reduces a stored charge.
Embodiments of the present invention capable of solving this problem will now be explained with reference to the drawings below.
FIGS.
1A to 1D are sectional views showing steps of a method of manufacturing a trench capacitor according to an embodiment of the present invention.
As shown in FIG.
1A, a mask pattern 2 is formed on a silicon substrate 1, and the silicon substrate is etched by the RIE method with the above mask pattern 2 used as a mask thereby to form a deep trench 3 in the silicon substrate 1.
A layered film consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film is used for the mask pattern 2.
The trench 3 is 6 .
mu.
m deep and has an aspect ratio of 10 or more



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