Electroless plating process and process for producing multilayer wiring board
An object of the present invention is to provide an electroless plating process capable of easily effecting sufficiently selective formation of a precise conductor pattern by irradiation with an energ... Read More
Inventors: Imura, Midori; Morijiri, Makoto; Hanazono, Masanobu; Kazui, Shinichi; Miura, Youzi; Ogino, Hiroyuki;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Monocrystalline silicon layers on substrates
OF THE INVENTION For a more complete understanding the invention will now be described in greater detail. As a substrate, materials well known in the semiconductor art may be employed: examples of su... Read More
Inventors: Ramesh, Subramanian; Martinez, Andre M.;, Assignee: North American Philips Corporation (New York, NY) |
Metallic fuse with optically absorptive layer
In accordance with the present invention, the disadvantages of prior metallic fuses for integrated circuits, as discussed above, have been overcome. The metallic fuse of the present invention, in one ... Read More
Inventors: McClure, Paul J.; Jones, Jr., Robert E.;, Assignee: INMOS Corporation (Colorado Springs, CO) |
Zone-melting recrystallization process
OF THE DRAWINGS FIG. 1 is a partially cut-away illustration of the ZMR heaters. FIGS. 2-5 are successive schematic cross-sectional views of the ZMR process. FIG. 6 is a flow chart of the improved ZMR... Read More
Inventors: Fan, John C. C.; Zavracky, Paul M.; Narayan, Jagdish; Allen, Lisa P.; Vu, Duy-Phach;, Assignee: Kopin Corporation (Taunton, MA) |
Method of forming improved encapsulation layer
The present invention provides a technique for overcoming the problems of the prior art SOI processes by providing a reliable crucible to contain the melt during thin film crystal growth of Si by form... Read More
Inventors: Baumgart, Helmut; Martinez, Andre;, Assignee: North American Philips Corp. (New York, NY) |
Capping technique for zone-melting recrystallization of insulated semiconductor films
The following description generally relates to silicon semiconductors. While silicon is by far the most important semiconductor material in use today, the invention is applicable by analogy in the ep... Read More
Inventors: Chen, Chenson K.; Tsaur, Bor-Yeu;, Assignee: Massachusetts Institute of Technology (Cambridge, MA) |
Buried channel heterojunction field effect transistor
The invention provides a field effect transistor that utilizes a narrow bandgap buried channel situated just below a heterojunction interface between a wide bandgap layer and a narrow bandgap layer. ... Read More
Inventors: Kiely, Philip A.; Taylor, Geoffrey W.;, Assignee: AT&T Bell Laboratories (Murray Hill, NJ) |
Quantum collector hot-electron transistor
Accordingly, it is an object of the present invention to provide a semiconductor device which maximizes the emitter to collector hot-electron transfer ratio in order to maximize the frequency of opera... Read More
Inventors: Choi, Kwong-Kit;, Assignee: The United States of America as represented by the Secretary of the Army (Washington, DC) |
Fast electrical complete turn-off optical device
It is the object of the invention to provide an optical device in which both center layers can be completely depleted, thereby resulting in the aforementioned trade-off being avoided. This objective i... Read More
Inventors: Kuijk, Maarten; Heremans, Paul; Vounckx, Roger; Borghs, Gustaaf;, Assignee: IMEC (Louvain, BE) |
Method for forming a bipolar transistor stabilized with electrical insulating elements
More specifically, an object of the invention is a heterojunction bipolar transistor based on III-V semiconductor materials comprising a collector, a base and an emitter and having a mesa located on t... Read More
Inventors: Delage, Sylvain; Cassette, Simone; Henkel, Achim; Salzenstein, Patrice;, Assignee: Thomson-CSF (Paris, FR) |
Modulation doped thyristor and complementary transistor combination for a monolithic optoelectronic integrated circuit
A semiconductor device structure and a fabrication technology have been invented to meet these objectives which achieves operation of vertical cavity devices as thyristor lasers and detectors together... Read More
Inventors: Taylor, Geoff W.;, Assignee: University of Connecticut (Farmington, CT) |
Fabrication of low resistance, non-alloyed, OHMIC contacts to INP using non-stoichiometric INP layers
OF THE INVENTION Experimental data demonstrates that low resistance non-alloyed ohmic contacts can be fabricated on undoped non-stoichiometric InP films which contain 0.6% of excess phosphorous. Non-... Read More
Inventors: Micovic, Miroslav; Docter, Daniel P.;, Assignee: HRL Laboratories, Inc. (Malibu, CA) |
Npn double heterostructure bipolar transistor with ingaasn base region
The present invention relates to an NPN double-heterojunction bipolar transistor (DHBT) formed on a gallium arsenide (GaAs) substrate (e.g. a semi-insulating GaAs substrate). The transistor comprises ... Read More
Inventors: Chang, Ping-Chih; Baca, Albert G.; Li, Nein-Yi; Hou, Hong Q.; Ashby, Carol I. H.;, Assignee: Sandia Corporation (Albuquerque, NM); Emcore Corporation (Somerset, NJ) |
Method for fabrication of high temperature superconductors
It is an object of the present invention to provide an article of manufacture and a method of making same in which a biaxially aligned c-axes inclined MgO platform supported on a substrate, which may ... Read More
Inventors: Balachandran, Uthamalingam; Ma, Beihai; Miller, Dean;, Assignee: The University of Chicago (Chicago, IL) |
Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
In accordance with the present invention, a flash electrically erasable programmable read only memory (EEPROM) and method of programming, reading and erasing the same are provided. In one embodiment, ... Read More
Inventors: Eitan, Boaz;, Assignee: Saifun Semiconductors Ltd. (Netanya, IL) |
Static random access memory cell utilizing a gated diode load element
In accordance with the preferred embodiment of the present invention, a memory cell is presented. The memory cell includes a gated diode as a load element. In addition, the memory cell includes a sele... Read More
Inventors: Nowak, Edward D.;, Assignee: VLSI Technology, Inc. (San Jose, CA) |
Apparatus and method for positionally enhancing an image
What is claimed is: 1. The method of correcting gate weave in a projector wherein each image of a series of frame or field images is initially situated near a known location with each said image of sa... Read More
Inventors: Cooper, J. Carl;, Assignee: |
Semicoductor device having a hetero interface with a lowered barrier
An object of this invention is to provide a semiconductor device capable of attaining the practical low-voltage operation by making it easy to inject carriers in a hetero interface, particularly an n-... Read More
Inventors: Saito, Shinji; Onomura, Masaaki; Nishikawa, Yukie; Ishikawa, Masayuki; Parbrook, Peter James;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Buried heterostructure laser with quaternary current blocking layer
OF PREFERRED EMBODIMENT FIG. 1 shows a schematic diagram of the buried heterostructure laser designed for a lasing wavelength of 1.55 .mu.m. On a heavily n-doped InP substrate 8 a series of epitaxial... Read More
Inventors: Knight, Douglas Gordon; Wu, Chunmeng;, Assignee: Nortel Networks Corporation (Montreal, CA) |
Suspended gate single-electron device
To address the above-discussed deficiencies of the prior art, the present invention provides a single-electron transistor device. The device comprises a source and drain located over a substrate and a... Read More
Inventors: Wasshuber, Christoph;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Charged particle beam lithography apparatus for forming pattern on semi-conductor
An object of the present invention is to solve the problems stated above and is to provide a charged particle beam lithography apparatus which remarkably increases the pattern number which can be sele... Read More
Inventors: Ito, Hiroyuki; Sohda, Yasunari; Someda, Yasuhiro; Nakayama, Yoshinori; Okumura, Masahide; Satoh, Hidetoshi;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Method and apparatus for sensing resistance values of memory cells
The present invention overcomes the problems associated with the prior art and provides a simplified and reliable method for sensing the resistance value of a resistor-based memory cell. A current is ... Read More
Inventors: Baker, R. Jacob;, Assignee: Micron Technology, Inc. (Boise, ID) |
Memory cell sensing integrator
The invention includes an apparatus and method for sensing logical states of memory cells that can withstand resistive variations of logic states associated with the memory cells. The system and metho... Read More
Inventors: Perner, Frederick; Tran, Lung;, Assignee: Hewlett-Packard Development Company, L.P. (Houston, TX) |
Line drivers that fit within a specified line pitch
The present invention provides a driver set that fits within a specified line pitch. The driver set includes a semiconductor substrate, a plurality of line driver groups, and a plurality of conductive... Read More
Inventors: Rinerson, Darrell; Chevallier, Christophe J.;, Assignee: Unity Semiconductor Corporation (Sunnyvale, CA) |
Dual-port random access memory having reduced architecture
It is an object of the present invention to provide a dual-port DRAM of reduced physical area. It is a further object of the present invention to provide a dual-port DRAM, having a number of array blo... Read More
Inventors: Reddy, Chitranjan N.; Poteet, Kenneth A.;, Assignee: Alliance Semiconductor Corporation (San Jose, CA) |
Embedded access trees for memory arrays
What is claimed is: 1. A circuit comprising: a select line; a bit line coupled to a memory cell; a bipolar transistor having a base coupled to the bit line; and a passive element coupled between the b... Read More
Inventors: Santoro, Mark R.; Tavrow, Lee S.; Bewick, Gary W.;, Assignee: Sun Microsystems, Inc. (Mountain View, CA) |
Erase method for page mode multiple bits-per-cell flash EEPROM
Accordingly, it is a general object of the present invention to provide an improved erasing method and circuitry for two bits-per-cell flash EEPROM cells which is relatively simple in its construction... Read More
Inventors: Bill, Colin Stewart; Su, Jonathan Shichang; Gutala, Ravi Prakash;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Semiconductor memory device
It is therefore an object of the present invention to provide a semiconductor memory device in which the accelerated biassing test can be achieved for all redundant cell columns without requiring any ... Read More
Inventors: Abe, Kazuhiko;, Assignee: NEC Corporation (JP) |
Data sequencing and registering in a four bit pre-fetch SDRAM
In FIG. 1, memory device 100 comprises a semiconductor integrated circuit encapsulated in a package 102. Metal conductive leads 104 extend from edges 106 and 108 of package 102. These leads 104 condu... Read More
Inventors: McAdams, Hugh P.; Thurston, Paulette; Nakamura, Masayuki;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Compensation capacitance for minimizing bit line coupling in multiport memory
Reference will now be made in detail to the presently preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Referring now to FIG. 1, a block diagram ... Read More
Inventors: Jung, Chang Ho;, Assignee: LSI Logic Corporation (Milpitas, CA) |
Active Solid-state 
