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Details
Inventors: Khorramabadi, Haideh;
Assignee: AT&T Bell Laboratories (Murray Hill, NJ)
Primary Examiner: Mottola; Steven
Assistant Examiner:
Attorney, Agent or Firm: Caplan; D. I.

An amplifier arrangement suitable for use as a line driver is built with a Class AB stage connected in parallel with a Class B stage, whereby the output currents of the stages are summed. Each of the Class AB and the Class B stages has an output current device that is connected in a common-source configuration. In a push-pull configuration of the arrangement, each of a pair of operational amplifiers in the Class AB stage separately drives each of a pair of operational amplifiers in the Class B stage.

DETAILED DESCRIPTION Referring now to the drawing, FIG.
1 shows an amplifier arrangement 100 having an input point 11 and an output point 12.
An output end of a preamplifier 10 is connected to the input point 11.
During operation, an input voltage signal V.
sub.
in is applied to the input point 11 by the preamplifier 10, whereby an output voltage signal V.
sub.
out is produced at the output point 12.
The output point 12 is electrically connected to an input point 16 of a utilization means 13, typically comprising a transmission line to be driven by the amplifier arrangement 100.
The amplifier arrangement 100 includes a pair of input amplifiers EP1 and EN1.
Each of these amplifiers has a positive output terminal that separately controls the gate electrode of a pair of series-connected auxiliary output transistors MAB1 and MAB2, respectively.
By themselves (in isolation from other circuitry), each of the amplifiers EP1 and EN1 typically is a conventional low-power Class A operational amplifier or an error amplifier.
During operation, each of these amplifiers operates in combination with its respective auxiliary output transistor MAB1 and MAB2 to achieve (push-pull) Class AB operation.
Thus the combination of the input amplifiers EP1 and EN1 with the auxiliary output transistors MAB1 and MAB2 forms an input Class AB stage of the amplifier arrangement 100.
The transistor MAB1 is PMOS; the transistor MAB2 is NMOS.
The high-current paths (source-drain paths) of these transistors are connected in series between power supply voltage terminals VDD and VSS.
Typically, the voltages applied to these terminals during operation of the arrangement 100 are +5v and 0v (ground), respectively.
The transistors MAB1 and MAB2 together form an auxiliary output device.
More specifically, the source terminal of the auxiliary PMOS transistor MAB1 is connected to a power supply voltage terminal (namely, VDD); hence this transistor MAB1 is connected in a common-source configuration.
Moreover, the source terminal of the auxiliary NMOS transistor MAB2 is connected to a power supply voltage terminal (namely, VSS); hence this transistor MAB2 is likewise connected in a common-source configuration



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