Application specific integrated circuit for a serial data bus

DETAILED DESCRIPTION FIG.
1 of the drawings illustrates a plurality of data communication devices, designated generally as 10, 10' .
.
.
10.
sup.
n, located on a serial data bus 12 of a data communication system, designated generally as 14.
Such data communication devices may include a portion of a computer, such as a transceiver chip, or a peripheral device such as a cursor control device (e.
g.
, a mouse or a trackball), a keyboard, a printer or a scanner.
As shown, devices 10-10.
sup.
n are serially interconnected for data transfer to one another by a common data bus 12.
The various devices are coupled to cable 12 by connection modules 16 which, in a preferred embodiment, contain a passive coupling transformer, resistive and capacitive circuits, and are known in the art for coupling each of the data processing and other devices to cable 12.
As will be described, the integrated circuit of a preferred embodiment permits synchronous serial communication and data transfer between devices 10-10.
sup.
n.
In a preferred embodiment, data is encoded as a ratio of low time to high time of each bit cell.
A bit cell boundary is defined by a falling edge on the bus.
A "0" is encoded as a bit cell in which the low time is greater than the high time.
Therefore, a "1" is defined as a bit cell in which the low time is less than the high time.
The period for each bit cell of the command signals and low speed data transmission is nominally 100 .
mu.
Sec.
.
+-.
30%.
For high speed data transmission, the bit cell is 25 .
mu.
Sec.
.
+-.
16%.
The format of a data transaction, whether receiving or transmitting, is a start bit, followed by up to 256 bits of data and ending with a stop bit.
FIG.
2 illustrates the protocol for providing transactions between a host computer and a specific device, such as a cursor control device, located on the serial data bus.
As shown in this figure, to signal the start of a command, an attention pulse is sent out on the serial data bus by a host computer.
An attention pulse is generated by the host computer by transmitting a bus low for a period of "T-attn