Automatic test equipment for integrated circuits

DETAILED DESCRIPTION We claim: 1.
An apparatus for testing an electronic circuit, comprising: means for connecting an electronic circuit having an operating condition which is to be tested to said apparatus, said electronic circuit havinq a plurality of selected node points; means for automatically applying an electrical interrogation signal to said selected circuit node points in turn; means for automatically obtaining from said circuit node points in response to said interrogation signal two electrical signal waveforms, one of which is a current waveform and the other of which is a voltage waveform, both of which have positive and negative portions, wherein said two waveforms, when combined, form an analog signature which is indicative of the operating condition of the electronic circuit relative to said circuit node points and wherein the apparatus includes means for combining said two waveforms to produce said analog signature; means for integrating the positive and negative portions of one cycle of each of said two waveforms; means for generating four digital values representative of the integrated portions, respectively, of said two waveforms; means establishing and storing reference digital values for the selected circuit node points; means comparing the generated digital values for each selected circuit node point with the corresponding reference digital values therefore and identifying those circuit node points having a generated digital value which is within a selected range relative to said corresponding reference digital value; and means for producing and displaying the analog signature for those circuit node points which do not have a generated digital value within said selected range.
2.
An apparatus of claim 1, wherein the circuit to be tested remains in-circuit and is in a power-off condition when tested, and wherein said interrogation signals are provided directly by the apparatus and not as a result of the circuit to be tested actually operating.
3.
An apparatus of claim 1, wherein the electronic circuit to be tested includes integrated circuits and said connecting means includes means providing separate connections for each pin of each integrated circuit in turn in said electronic circuit