BiMOS semiconductor integrated circuit having short-circuit protection

DETAILED DESCRIPTION The object of the present invention is to provide a BiMOS semiconductor integrated circuit having an output circuit capable of removing, from the Darlington circuit during normal operation, rise current limitations, thus realizing a high speed operation, while an amount of current flowing in the transistors constituting the Darlington circuit at the short circuit state of the output terminal, is restricted so as to secure the bonding wires thereof.
The present invention provides a BiMOS semiconductor integrated circuit including a plurality of bipolar transistors and at least one field effect transistor formed on a common semiconductor chip.
The bipolar transistors form a Darlington circuit for providing a high voltage level at an output node of the circuit.
The field effect transistor can be either a P-channel or an N-channel field effect transistor.
According to a first embodiment of the present invention, a P-channel field effect transistor has the source connected to the base of an NPN transistor on the input side of a Darlington circuit and the gate and a drain commonly connected to the emitter of an NPN transistor on the output side of the Darlington circuit.
In operation of the output circuit according to the present invention, the P-channel transistor is turned `ON` when the output node of the Darlington circuit is unfavourably grounded while in a high voltage level operation, thus limiting the current flowing through the Darlington circuit, and also a low level output supply circuit is provided for supplying a low voltage level to the output node.
Furthermore, according to a second embodiment of the present invention, the field effect transistor is an N-channel MOS transistor having the gate and the drain commonly connected to the base of the NPN transistor on the input side of the Darlington circuit and the source connected to the emitter of the NPN transistor on the output side of the Darlington circuit, and a low level output supply circuit is provided for supplying a low voltage level to the output node