Bias adjustment responsive to signal power

DETAILED DESCRIPTION What is claimed is: 1.
An improved base-emitter bias voltage correction arrangement for a power transistor adapted for processing signals carrying modulation which produces a varying average power level, which modulation perturbs the base-emitter offset voltage of said transistor and results in increased distortion, the arrangement comprising: bias means having a first input terminal coupled with the base-emitter junction of the transistor and also having an output terminal, said first input terminal of said bias means being coupled to a voltage source for producing a base-emitter bias voltage for biasing said transistor into a low-distortion conduction condition, said output terminal coupling said base-emitter bias voltage to said base-emitter junction for maintaining said base-emitter bias voltage at low frequencies notwithstanding the effects of application of input signals to said base-emitter junction; the improvement comprising; envelope detection means coupled to the signal path for producing a baseband replica of the modulation; a second input terminal of said bias means; signal processing means coupling said envelope detection means with said second input terminal of said bias means for processing said replica of said modulation for producing a second bias control signal; and wherein said improvement further lies in that said second bias control signal coupled to said second input terminal of said bias means is superposed upon said base-emitter bias voltage thereby varying said base-emitter bias voltage as a function of said modulation for compensating said base-emitter bias voltage for the changes in the base-emitter offset voltage resulting from the power changes resulting from said modulation whereby said low-distortion conduction condition is maintained.
2.
An arrangement according to claim 1 wherein said signal processing means is responsive to the time rate of change of said signal power level.
3.
An arrangement according to claim 1 or 2 wherein said transistor is a bipolar transistor, and said bias means increases said base-emitter bias applied to said base-emitter junction of said transistor when the signal power coupled to the load on said transistor is reduced