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Buffer circuit
| Details |
Inventors: Matsuzawa, Akira;
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Primary Examiner: Mottola; Steven
Assistant Examiner:
Attorney, Agent or Firm: Stevens, Davis, Miller & Mosher
A buffer circuit includes an operational amplifier circuit, a first emitter follower circuit whose base is driven by an output of the operational amplifier circuit and whose output is fed back to an inverting input terminal of the operational amplifier circuit, and a second emitter follower circuit whose base is also driven by the output of the operational amplifier circuit and whose output drives a load circuit. In another form, the buffer circuit also includes a current control circuit that detects operation current flowing through the second emitter follower circuit, thereby controlling the operation current flowing through the first emitter follower circuit. |
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DETAILED DESCRIPTION With a view to solve the prior art problem described above, it is an object of the present invention to provide a buffer circuit which can operate with a satisfactory settling characteristic without causing occurrence of objectionable ringing.
The present invention which solves the prior art problem provides a buffer circuit comprising an operational amplifier circuit, a first emitter follower circuit whose base is driven by the output of the operational amplifier circuit, and a second emitter follower circuit whose base is also driven by the output of the operational amplifier circuit, the output of the first emitter follower circuit being fed back to an inverting input terminal of the operational amplifier circuit, and the output of the second emitter follower circuit driving a load circuit.
In the buffer circuit of the present invention having the structure described above, the capacitive load is not directly connected to the feedback circuit system for the operational amplifier.
Therefore, no change occurs in both the gain of the feedback circuit system and the signal phase fed back through the feedback circuit system, so that neither ringing nor oscillation can occur.
Also, the d.
c.
level of the signal fed back from the first emitter follower circuit to the inverting input terminal of the operational amplifier circuit and the d.
c.
level of the output signal of the second emitter follower circuit differ from each other only by an amount corresponding to the potential difference between the base-emitter voltages of the two transistors forming these two emitter follower circuits respectively.
That is, these two d.
c.
levels are practically substantially equal to each other, and any large offset voltage does not appear between the input and output signals.
Therefore, the buffer circuit of the present invention can operate with a satisfactory settling characteristic.
As described above, the buffer circuit according to the present invention comprises an operational amplifier circuit, a first emitter follower circuit whose base is driven by the output of the operational amplifier circuit, and a second emitter follower circuit whose base is also driven by the output of the operational amplifier circuit, the output of the first emitter follower circuit being fed back to an inverting input terminal of the operational amplifier circuit, and the output of the second emitter follower circuit driving a load circuit
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Audio Signal Processing 
