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Home Audio Signal Processing Combined-deemphasis-circuit-and-noise-blanker

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 Combined deemphasis circuit and noise blanker

Details
Inventors: Kennedy, Richard A.; Manlove, Gregory J.; Marrah, Jeffrey J.; Zarabadi, Seyed R.;
Assignee: Delco Electronics Corporation (Kokomo, IN)
Primary Examiner: Isen; Forester W.
Assistant Examiner:
Attorney, Agent or Firm: Duke; Albert F.

An FM stereo radio circuit has an ultrasonic noise detector and an amplitude noise detector each for detecting impulse noise by developing an average noise signal and comparing the average noise signal with an attenuated value of the instantaneous noise signal to generate a noise flag. A dual mode circuit normally operates as a low pass filter for a deemphasis function and is switched by the noise flag to operate as a sample and hold circuit which blanks the noise pulse. The dual mode circuit uses a switched capacitance design and is driven by clock signals to serve as a filter. The clock signals are stopped by the noise flag to effect the sample and hold function.

DETAILED DESCRIPTION It is therefore an object of the invention to provide a noise reduction circuit to an FM radio for eliminating short duration impulse noises.
One aspect of this object is to efficiently detect such noise without negative impact on the circuit, and another aspect is to make the noise reduction in a deemphasis circuit with no significant addition to the circuit.
The invention is carried out in an FM stereo radio circuit by a combined noise blanker and deemphasis circuit comprising, a flag generating circuit responsive to the FM composite signal for detecting a short duration noise pulse and generating a flag for the duration of the noise, demodulator means for producing a stereo demodulated signal, a dual mode circuit coupled to the demodulator means to receive the demodulated signal and effective to operate in a first mode as a low pass filter and in a second mode as a sample and hold circuit, and control means coupled to the flag generating circuit for normally operating the dual mode circuit as a low pass filter to serve as a deemphasis circuit and responsive to a flag for switching to the second mode to sample the filtered signal that was present at the moment of switching and hold the sampled signal for the duration of the flag so that the noise pulse does not pass through the dual mode circuit.



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