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 Decoder for self-clocking serial data communications

Details
Inventors: Stewart, Robert E.;
Assignee:
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:

Apparatus for decoding a self-clocking, encoded signal wherein a series of data bits is encoded such that for each data bit, the encoded signal contains a first transition, and, for each data bit for which the succeeding data bit has the same binary value, the encoded signal contains a second transition occurring within a predetermined time interval after the first transition. The decoding apparatus comprises storage means responsive to a clocking signal of at least a predetermined minimum pulse width, received at a clock input for storing a sample of a digital signal received at a data input, the storage means having at least one output indicative of the stored value; an exclusive-OR gate; a first signal path from the output of the storage means through the exclusive-OR gate to the clock input of the storage means; a second signal path from the source of the encoded signal through the exclusive-OR gate to the clock input of the storage means; and a third signal path from the source of the encoded signal to the data input of the storage means; the time for a signal to propagate along the first signal path being at least as long as the minimum pulse width required to clock the storage means; and the difference between the time for a signal to propagate along the second signal path and the time for a signal to propagate along the third signal path being at least as long as said predetermined time interval.

DETAILED DESCRIPTION To attain these and other objectives, at the receiving end of at least one serial data channel to which a receiving device connects, this invention provides simple but highly efficient and effective receiving interface circuitry for such a link.
The interface circuitry comprises and centers around a decoder for connecting to the channel and separating from the composite signal on the channel the component data bits and clocking signals; a carrier detector, also adapted for connecting to the channel and for detecting the presence of information on the channel, and in response thereto, for enabling a serial shift register to receive serially the transmitted data bits in response to the clocking signals; and an internal clock synchronizer for synchronizing the occurrences of parallel transfers of data bits to the receiving device with the occurrence of a predetermined number of serial data bits at the beginning of the transfer of serial data from the channel.
The decoder is elegant in its simplicity.
It employs a flip-flop, an exclusive-OR gate, and a minimum of two delay elements.
the delays cause the flip flop to sample the composite signal about one-quarter way through each bit cell.
The carrier detector is also quite simple.
The bus signal is compared against a preset threshold.
If the bus signal exceeds the threshold, a pulse train is generated.
The pulses set a latch.
The trailing edge of a lower frequency internal clock causes the latch to clear if the bus signal vanishes.
An internal clock is provided, independently of the clock derived from received data.
One time at the beginning of each message, the synchronization character is detected in the incoming message, and the phase of the internal clock circuit is corrected.
It is this clock which controls the transfers from the interface to a host device.
Other objectives, advantages and features of the invention will become apparent upon review of the succeeding description of an illustrative embodiment taken in connection with the accompanying drawings



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