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 Detecting redundant digital codewords using a variable criterion

Details
Inventors: Grande, Johannes; Brown, James H.;
Assignee: Rockwell International Corporation (El Segundo, CA)
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Taken; Michael E., Sewell; V. Lawrence, Greenberg; Howard R.

Fast response detection of repeatedly transmitted redundant digital codewords is provided by checking the same bit-position in consecutive n bit codewords. The number m of codewords checked is increased until the number of equal bit values reaches a varying threshold j.sub.m dependent upon m, or until m reaches a maximum M. This sequence is repeated for each of the remaining bit-positions of the codeword. Faster response is provided when an early threshold is reached, eliminating the need to continue checking the same bit-position in the remainder of the M codewords.

DETAILED DESCRIPTION FIG.
1 shows a digital codeword detector generally designated 10.
Data from transmission line 12 is received by a receive unit 14.
This receive unit is known in the art, and will only be briefly described.
A clock recovery circuit 16, such as a phase locked loop, extracts the clock signals from the data.
These clock signals are delivered to a retime circuit 18, such as a retime flip-flop, to retime or synchronize the data to the recovered clock.
The extracted clock signals from circuit 16 are also delivered to a state controller 20 which outputs framing configuration and bit sequencing identification on bus 22.
The extracted clock signals from circuit 16 are also delivered on output clock line 24.
Buses 22 and 24 are connected to the remaining circuitry, to be described, for bit sequencing and clocking.
The data on line 12 may be either serial or parallel.
In some applications involving high speed serial or parallel data on transmission line 12, a demultiplexing unit, not shown, may be provided at the output of circuit 18 to output a plurality of parallel data channels as controlled and timed by the bit sequencing and framing configuration identification from state controller 20.
The data output on bus 26 may be serial or parallel.
Data from receive unit 14 is stored in a codeword memory 28 having a capacity n.
times.
M, where n is the number of bits in a codeword and M is a number of consecutive codewords in a given framing format or configuration.
The framing configuration identification output on bus 22 from state controller 20 provides group synchronization signals, and provides word synchronization signals for noncyclic codes.
These synchronization signals control bit sequencing for identifying the codeword bit-positions of the received group of data bits, and control entry into memory 28.
The codeword bit-positions are either absolute (for noncyclic codes) or relative to an arbitrarily chosen start of a codeword (cyclic codes).
Codeword memory 28 is any form of storage which can be accessed for storage and retrieval of data, e



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