DETAILED DESCRIPTION OF THE INVENTION The concepts underlying the present invention are best illustrated by an example.
In particular, consideration is given to the addition of two 16-bit numbers.
The basic functional unit for performing addition of binary digits is a one-bit full adder, such as that shown in FIG 1.
In particular, full adder 10 accepts two operand input bits A and B and produces an output bit S.
sub.
out.
Additionally, full adder 10 also accepts a carry input signal C.
sub.
in which is also used in generating the output sum S.
sub.
out and the carry output signal C.
sub.
out in accordance with the logic of binary arithmetic.
Since the carry output signal is supplied to the next higher bit position, it is said to have weight two.
The addition of two 16-bit numbers requires that at least 16 addition operations be performed, and that the output carry of each addition be used as the input carry to a full adder which is performing addition of operand bits of the next higher weight.
The fully parallel solution to this problem is to provide 16 full adders 10a, 10b, .
.
.
, 10p (chained together as far as ripple carry is concerned) to perform the addition of bits of all weights essentially simultaneously, as shown in system 20 in FIG.
2.
Here A.
sub.
0, A.
sub.
1, A.
sub.
2, A.
sub.
3, A.
sub.
4, A.
sub.
5, A.
sub.
6, A.
sub.
7, A.
sub.
8, A.
sub.
9, A.
sub.
10, A.
sub.
11, A.
sub.
12, A.
sub.
13, A.
sub.
14 and A.
sub.
15 are progressively more significant bits of a first sixteen-bit operand A and B.
sub.
0, B.
sub.
1, B.
sub.
2, B.
sub.
3, B.
sub.
4, B.
sub.
5, B.
sub.
6, B.
sub.
7, B.
sub.
8, B.
sub.
9, B.
sub.
10, B.
sub.
11, B.
sub.
12, B.
sub.
13, B.
sub.
14 and B.
sub.
15 are progressively more significant bits of a second sixteen-bit operand B.
Since the carry output from one stage can affect the carry at the next stage, it takes a certain amount of time for the circuit to fully resolve the correct output, as the carry from each stage is finalized.
The entire addition is usually thought of as occurring in one clock cycle.
It is noted that while there exist certain hardware solutions to speed up the circuit shown in FIG
|
Audio Signal Processing 
