Digital echo suppressor

DETAILED DESCRIPTION The echo suppressor of the present invention operates on digital signals representing the signal on the receive and send lines to determine when interruption of the send line should take place.
The send line and receive line signals are multiplexed into a single A/D converter thereby saving on conversion logic.
A true/complement logic system operates on the A/D output signals to cause all receive line signals to be of one sign and all send line signals to be of the opposite sign.
If the sum of the receive line signals over a period of time exceeds a threshold value an interrupt switch is thrown in the send line for a given overhang period.
Break-in logic is included to override the interrupt switch under certain conditions.
The receive and send line signals from the true/complement logic system are summed over a period of time and the sign of the sum is temporarily stored.
When a given number of the signs stored during a predetermined number of successive time periods indicate the send line signals exceed the receive line signals, the break-in operation throws a switch in the send line to bypass the interrupt switch.
Also, the break-in logic just described throws an attenuate switch in the receive line to add a 6dB loss to the receive line signals.
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