Field programmable gate arrays

DETAILED DESCRIPTION Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims.
Features of the dependent claims may be combined with those of the independent claims as appropriate and in combinations other than those explicitly set out in the claims.
According to a first aspect of the invention there is provided a field programmable gate array designed to receive encrypted configuration data and having on its input side decryption logic for acting on the encrypted configuration data received on reconfiguration, e.
g.
on power-up, to decrypt it.
The decrypted configuration data can then be handled within the field programmable gate array in a conventional manner, i.
e.
distributed to configure the logical structure of the functional portion of the field programmable gate array.
In an embodiment of the invention, the decryption logic accesses a decryption key stored within the FPGA.
The decryption algorithm then uses the key as an operand.
The decryption algorithm is preferably stateful rather than stateless.
A stateful algorithm may be realized in hardware based on a standard linear feedback shift register (LFSR) design.
Typically, the key memory will be formed of non-volatile memory elements, for example EEPROM, and the functional portion of the gate array will be formed of volatile elements, for example SRAM.
The key size may be typically of the order of 1K bits or more, with the size being chosen to provide the desired data security level having regard to current code cracking technology.
Smaller key sizes may be appropriate for some applications, for example 64 bits, 128 bits or 256 bits.
Since the key memory will typically only constitute a small fraction of the FPGA in comparison to the gate array of the functional portion of the FPGA, the key memory can be realized in the hardware with a relatively large feature size which is beneficial to yields.
According to a second aspect of the invention there is provided a method of processing field programmable gate array configuration data