Integrated circuit with memory comprising a fraud-prevention device

DETAILED DESCRIPTION An object of the invention therefore is an integrated circuit comprising an electrically erasable programmable memory, the cells of which comprise a transistor with floating gate which is series connected with an access transistor, wherein, in order to prevent deterioration in the information stored in the transistors with floating gates due to excessive read voltage being applied to the cell, the circuit has an additional cell constituted like the other cells and programmed in a state where its transistor with floating gate cannot be made conductive, the gate and the source of the transistor with floating gate of the additional cell being grounded, the drain and the gate of the access transistor receiving the memory reading voltage, and a threshold comparator connected to the drain of the floating gate transistor to compare the voltage on this drain with the reading voltage and to give a signal in the event of any abnormal drop in the voltage at the drain.