Audio signal processing apparatus |
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Linear phase response multi-way speaker system |
| What is claimed is: 1. A multi-way speaker system comprising a low pass filter, a high pass filter ... |
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Sound reproducing with remote amplifying transducer |
| OF PREFERRED EMBODIMENTS With reference now to the drawing and more particularly FIG. 1 thereof, ... |
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Audio signal processing system |
| What is claimed is: 1. An audio signal processing system of the type for generating ambient effects,... |
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Method of improving the acoustics of a hall |
| I claim: 1. A method of improving the acoustics of a room having a performance area in which sound ... |
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Cabinet for loudspeaker |
| It is an object of the present invention to provide a cabinet for a loudspeaker, that does not ... |
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Loudspeaker structure |
| I claim: 1. An electro acoustical transducer structure, comprising; (a) a base enclosure of ... |
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Stereo electroacoustical transducing |
| What is claimed is: 1. Stereo electroacoustical transducing apparatus comprising, dual-channel ... |
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Multiple chamber loudspeaker system |
| It is an important object of this invention to provide an improved dual-chamber ported loudspeaker ... |
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Speaker system |
| An object of the present invention is to provide a speaker system which can be installed in a ... |
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Interface circuit for connecting a digital equipment to a time multiplex link
| Details |
Inventors: Gass, Raymond; Ruhlmann, Andre;
Assignee: La Telephonie Industrielle et Commerciale Telic Alcatel (Strasbourg, FR)
Primary Examiner: Olms; Douglas W.
Assistant Examiner: Chin; Wellington
Attorney, Agent or Firm: Sughrue, Mion, Zinn, Macpeak & Seas
The invention relates to an interface circuit for connecting a digital equipment (2) for sending and receiving data to a time multiplex link (3). The connection interface circuit is provided with a bit send terminal (3E1) and a bit receive terminal (3R1) for connection to the corresponding wires (3E, 3R) of a time multiplex link (3) in parallel with other interface circuits (1 or 8) of equipments for transmitting and receiving digital data (2) or speech signals (4). The interface circuit includes a synchronization arrangement (12) enabling it to be connected to the multiplex link (3) in a manner identical to that provided for the interface circuit (8) of the transmitter/receiver equipments for speech signals (4) and to adapt itself automatically to the bit rate capabilities offered by the multiplex link. The interface circuit further includes transmit and receive register groups as well as a buffer register group disposed between the transmit and receive registers and a microprocessor of the digital equipment. Also included is a control arrangement for simultaneously driving the transmit and receive registers in connection with the synchronization arrangement, and for driving the buffer registers under the control of the microprocessor of the digital equipment. |
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DETAILED DESCRIPTION The present invention thus provides an interface circuit for connecting a digital equipment, at least partially under its own control, for transmitting and receiving digital data to a two-way time multiplex link suitable for transmitting, in byte form, digital data or speech signals converted into a suitable binary form by specialized interface circuits connected in parallel to the time muItiplex link, under the control of a clock module governing byte transmission and receptio by means of clock signals and synchronization signals which are associated with the different time slots available during each frame of the time multiplex link. According to a characteristic of the invention, said connection interface circuit being provided with a bit transmission terminal and a bit reception terminal enabling it to be connected to the corresponding wires of the time multiplex link in parallel with other interface circuits of equipments for transmitting and receiving digital data or speech signals, includes a synchronization arrangement comprising firstly a local clock generator suitable for receiving from the clook module both a common clock signal and a link bit rate controlling clock signal whose frequency is equal to the frequency of the common clock signal or to a submultiple thereof, and secondly two time slot selection units, one for transmission and the other for reception suitable for receiving the corresponding synchronization signals, in such a manner as to obtain a connection between the connection interface circuit and the time multiplex link which is identical to the connection provided for the interface circuits for converting speech signals, and for automatically adapting to the bit rate capacity provided by the selected time multiplex link.
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