Method and apparatus for monitoring a pulse-code modulated data transmission

DETAILED DESCRIPTION OF THE DRAWINGS The invention will now be described, by way of example, with reference to FIGS.
1 and 2.
The pulse code modulated message T (FIG.
1(c)), which arrives distorted due to interference, is compared with the undistorted time zones S (FIG.
1(a)), derived at the receiver 10.
The phases of the edges of the pulse code modulated message T (FIG.
1(c)), which arrive distorted due to interference, are compared with the phases of the edges of the undistorted message S (FIG.
1(a)) derived at the receiver 10.
The phases of the edges of the undistorted message S are synthesized at the receiver 10 from the incoming message by means of a known synchronizing circuit SYNC (FIG.
2), e.
g.
by flywheel synchronization with phase correction for the locally produced clock C.
The synchronizing circuit SYNC, which subdivides the locally generated fast clock signal C while taking into consideration the phases of the incoming pulse edges of message T, generates a plurality of sampling pulses U (FIG.
1(b)) which control the transfer of the received message T into the series/parallel register SPR.
Each sampling pulse U is preferably, but not necessarily, generated in the middle of each pulse of the desired pulse path S and is applied to register SPR to clock the incoming pulses T into register SPR.
The synchronizing circuit SYNC has several terminals by means of which a time zone A around the theoretical pulse edge instants is selected via the distortion zone selectors VBS.
Both the beginning and the end of the selected time zone A is determined by the signals a.
sub.
1 and a.
sub.
2, respectively, which signals control the flip-flop FF1.
The time zone A preferably, but not necessarily, extends symmetrically around the theoretical edge instants.
The distortion tolerance zones A and A are shown in FIG.
1(d).
These zones define the preselected distortion tolerance limits.
If, during the time zone determined by the state A of flip-flop FF1, at least one of the pulse edges derived from the edge detector circuit comprising flip-flops FF4, FF5 and EXCLUSIVE OR gate G1 arrives, as has been assumed in FIG