Oscillator frequency control arrangement for a stereo decoder

DETAILED DESCRIPTION What is claimed: 1.
A stereo decoder apparatus responsive to an analog composite signal containing audio information that includes a pilot signal component, comprising: a controllable oscillator responsive to an analog first control signal, said oscillator generating an oscillatory signal at a frequency that is controlled in accordance with said first control signal; sampling means responsive to said analog composite signal for sampling said composite signal to generate therefrom a bit weighted sampled signal having a first plurality of bits that represent said composite signal in a numerical, bit weighted form and that contains synchronization information of said pilot signal component; means responsive to said sampled signal and to said oscillatory signal for generating, a phase error indicative signal that forms a digital word having a second plurality of bits with a numerical bit weighted value that is indicative of a phase difference between said pilot signal component and said oscillatory signal; a source of a first current; a capacitance; a controllable means responsive to a second control signal that is coupled to a control terminal thereof for coupling said first current to said capacitance for a given interval; and means responsive to said second plurality of bits of said phase error indicative signal for generating said second control signal in a manner that varies a length of said given interval in which said first current is coupled to said capacitance so as to develop said analog first control signal in said capacitance.
2.
An apparatus according to claim 1 wherein said controllable oscillator includes an FET transistor having a gate electrode thereof coupled to said first control signal such that a high input impedance of said FET transistor prevents a charge in said capacitance from changing outside said given interval.
3.
An apparatus according to claim 1 wherein said second control signal generating means comprises a counter that is preset in accordance with a value of said phase error indicative signal, wherein said counter is responsive to a clock signal and counts pulses of said clock signal during said given interval and wherein said second control signal is generated as long as said counter counts said pulses of said clock signal