Parametric tester for semiconductor devices

DETAILED DESCRIPTION The present invention comprises a tester for conducting parametric tests on a digital semiconductor device through its external leads.
Tests are conducted by applying a known voltage to a particular input lead and determining whether more current is drawn by the lead than is allowable for an acceptable device.
The device comprises a current source means electrically coupled to a particular lead of the device under test for supplying a constant current to the lead, a voltage maintenance means electrically coupled to the lead for maintaining the lead at a specified voltage, and current direction-sensing means electrically coupled between the voltage maintenance means and the lead to detect the direction of current flow between the voltage maintenance means and the lead, thereby determining whether the lead draws more or less current than the constant current.
If the constant current is set at a maximum current which should be drawn by the device at the set voltage, then a net current flow from the voltage maintenance means to the particular lead will occur for an unacceptable device, whereas a net current flow toward the voltage maintenance means will signify that the lead under test is drawing less current than the maximum specified current and, therefore, the particular lead passes the parametric test.
In a preferred embodiment, the direction-sensing means of the present invention comprises a non-linear bidirectional load electrically coupled between the lead under test and the voltage maintenance means; a voltage comparator whose inputs are electrically coupled to respective ones of the terminals of the bidirectional load, and an error detector electrically coupled to the output of the voltage comparator to determine whether the output of the voltage comparator signifies a net flow into the lead or towards the voltage maintenance means.