Pseudorandom noise code generator

DETAILED DESCRIPTION In order to attain the object, an inventive pseudorandom noise code generator is characterized in the use of a simple type or modular type shift register generator; exclusive logic sum gates at respective stages in which outputs of flipflops forming the simple type or modular type shift register generator and an external maximal sequence code are entered; and a plurality of flipflops whose outputs are controlled by a clock and in which outputs of said exclusive logic sum gates are entered.
There are two known basic arrangements of maximal sequence code generator as shown in FIG.
2.
In FIG.
2(a), outputs of respective flipflops D-FF.
sub.
l through D-FF.
sub.
n are selected by switches SW.
sub.
2 to SW.
sub.
n, and their exclusive logic sum is obtained, fed back to the first stage flipflop.
In FIG.
2(b), the output of the final stage flipflop is selected by the switches SW.
sub.
2 to SW.
sub.
n The exclusive logic sum of the selected output and an output of the flipflop at the preceding stage is obtained, and it is entered in respective flipflops.
In general, the former is called a "simple type shift register generator" and the latter is called a "modular type shift register generator".
The modular type shift register generator is more advantageous for speed-up purposes because an increase in the number of stages of the shift register of the simple type shift register generator invites an increase in the number of stages of exclusive logic sum gates in the feedback route and invites an increase in the delay time (reference document: R.
C Dixon, Spread Spectrum Systems, pp.
53-92, John Wiley & Sons, 1976).
The invention proposes a system which uses a simple type shift register generator and a modular type shift register generator to enable simultaneous generation of a plurality of GOLD codes.