DETAILED DESCRIPTION We claim: 1.
A recognition procedure including the steps of teaching a reference pattern to a machine-based recognition system by writing a first binary digit to each of a plurality of addressable data stores, each of which has a plurality of addressable data storage locations, at locations selected by applying respective sets of values as addresses to the addressable data stores, where the sets of values represent characteristics of parts of the reference pattern, writing a second binary digit to all locations not selected in the addressable data stores, and of measuring another pattern against the reference pattern by applying, as addresses, to the addressable data stores, sets of values representing characteristics of parts of the other pattern, where the parts correspond to the said parts of the reference pattern, reading the contents of those locations selected, applying the binary digits read from the selected locations to a network that provides an output signal representing one binary digit as its output only when the first binary digit is obtained from each selected location, and which provides an output signal representing the other binary digit if one second binary digit is obtained from the selected locations, forming at least one sum of the total number of occurrences of the first binary digit at selected positions within the network, and providing a result signal indicating the result of the measurement, where the result signal is determined by the output signal from the network and the sum of the total number of occurrences of the first binary digit at selected positions within the network.
2.
A recognition procedure as claimed in claim 1, wherein the first binary digit is a logical 1, and the network for providing the output signal is a network of logical AND gates.
3.
A recognition procedure as claimed in claim 1, wherein the first binary digit is a logical 1, and the network includes a logic element capable of performing an AND operation on values presented to it, associated latches for storing respective input and output values for the logic element, and counters for controlling the grouping, and circulation, of successive input and output values, through the logic element, in group sizes, and for a number of times, as set by initial settings of the counters
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Audio Signal Processing 
