Serial scan diagnostics apparatus and method for a memory device

Details

Inventors: Lyon, Terry L.; Chritz, Jeff;
Assignee: National Semiconductor Corporation (Santa Clara, CA); Control Data Corporation (Minneapolis, MN)
Primary Examiner: Atkinson; Charles E.
Assistant Examiner:
Attorney, Agent or Firm: Rappaport; Irving S., Colwell; Robert C., Hughes; Richard L.

A scan diagnostics apparatus and method is useful in connection with the memory integrated circuit. A shift register is provided which can receive data in parallel from the input register and output the data serially. The shift register can receive serial data and output in parallel either to the input buffer or the output buffer. Preferably the shift register can receive in parallel, data from the output buffer and output the data serially.

DETAILED DESCRIPTION The present invention includes scan diagnostics circuitry useful in connection with a memory chip.
The scan diagnostics circuitry preferably includes a serial scan shift register.
In one embodiment of the invention, input signals which are received in the input register are provided to both the memory control circuitry and the shift register and are placed in the shift register in parallel, after which the input signals are serially output onto the serial output line of the shift register.
In this way the state of the input register is captured in the shift register.
The captured state of the input register can then be serially shifted out for analysis by, e.
g.
, diagnostics circuitry.
Capturing the state of the input register is useful, e.
g.
, in determining whether addresses and/or data that were sent to a memory chip were changed before their receipt in the input buffer.
By comparing data and/or addresses sent to the memory chip with the data and/or addresses received in the memory chip, transmission errors can be detected.
According to a further embodiment of the invention, control information is shifted into the shift register in serial fashion and output in parallel to the input register of the memory IC in order to permit forcing a desired set of input signals into the input register.
Forcing the state of the input register (i.
e.
placing a known set of data in the input register) is useful, e.
g.
, when an error has been discovered in a computer system and it is unknown whether the error occurred before signals arrived at a given IC or after such arrival.
For example, a given IC may be known to produce errors when a write operation is performed on a given memory location.
Such an error might, however, arise from erroneous signals arriving at the input register or from erroneous handling of correct signals.
By forcing the state of the input register, it is known that the correct signals have arrived at the input register.
Thus if the error occurs in response to a forced-input write of that memory location, it can be determined that the error lies in the operation of the integrated circuit and not prior to the receipt of data in the input register

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