Wafer indexing system using a grid pattern and coding and orientation marks in each grid cell

DETAILED DESCRIPTION It is a primary object of this invention to provide a wafer with an indexing and mapping system.
It is another primary object of this invention to provide a system for accurately locating artifacts and defects on a wafer.
It is another object of this invention to permanently locate an artifact on a wafer for subsequent analysis to determine whether it is a defect.
It is still another object of this invention to permanently locate structural components on a wafer.
It is yet still another object of this invention to retain the identity of a chip on a wafer regardless of the orientation of the wafer.
It is a further object of this invention to retain the identity of a particular chip in the wafer after the wafer has been diced.
It is another further object of this invention to have a coding system built into the chip suitable for use before or after the wafer has been diced.
It is still another further object of this invention to provide an indexing system that could be used to control the process automation of chips.
It is yet still another further object of this invention to provide a means for determining the size of artifacts, device line widths and device gap widths.
These and other objects are accomplished by applying a permanent micrometer grid pattern to the backside of the wafer, for example, a transparent bubble wafer.
In a preferred embodiment, the grid pattern is photolithographically produced by chemical or sputter etching onto the backside of the wafer.
An alternative method is to deposit a thin film of platinum or another noble metal and etch the grid pattern in the metal.
In a preferred embodiment, the grid pattern consists of an array of a plurality of uniform size cells, for example, 40 unit cells wide by 40 unit cells long.
Each unit cell is 1 millimeter square and has each side divided into ten units.
Each unit cell includes a coding system, for example, a digital coding arrangement to identify the row and column of each cell in the grid pattern.
The grid pattern has orientation lines or bars to align the grid pattern with respect to the wafer flats