Absolute difference processor element processing unit, and processor

DETAILED DESCRIPTION An object of the present invention is accordingly to enable a single processor element to compute an absolute difference.
Another object of the invention is to enable a single processor element to compute a cumulative absolute difference.
Still another object is to perform multiplication by a processing unit comprising a plurality of processor elements which can also compute cumulative absolute differences individually, in parallel.
Yet another object is to compute an inner product by means of this processing unit.
A further object is to perform matrix multiplication efficiently.
A processor element comprises a shifter for shifting first input data by a controllable number of bits, first input means for selecting the shifted first input data or first result data, and second input means for selecting second input data or second result data.
An arithmetic means controllably adds or subtracts the outputs of the first and second input means to produce the first and second result data.
A first register stores the first result data for provision to the first input means.
A second register stores the second result data for provision to the second input means, and for external output.
A processing unit comprises an input bus group, an output bus group, a plurality of the above processor elements connected in parallel between the input bus group and the output bus group, and a last-stage accumulator connected to the output bus group.
A processor comprises a plurality of the above processing units connected in parallel between an input bus group and an output bus group.