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Address-translation-unit-supporting-variable-page-sizes

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Address translation unit supporting variable page sizes

Details

Inventors: Kang, Hoai Sig;
Assignee: Hyundai Electronics Industries Co., Ltd. (Ichon-shi, KR)
Primary Examiner: Yoo; Do
Assistant Examiner: McLean; Kimberly
Attorney, Agent or Firm: Jacobson, Price, Holman & Stern, PLLC

An address translation unit for supporting multiple page modes, with each page mode having a different page size. The address translation unit includes a tag interface unit for outputting effective tag data in response to a page mode select signal, a tag memory for storing tag data and for comparing the effective tag data with previously stored tag data to generate a comparison signal in response to a word signal and a write control signal, a data interface unit for outputting effective physical data in response to the page mode select signal, a data memory for storing effective physical data from the data interface unit and for outputting a converted physical address in response to the word signal, the write control signal and the comparison signal, a decoder interface unit for receiving a part of a linear address in response to a page mode signal and for outputting the part of the linear address as an entry index signal, and a decoding unit for decoding the part of the linear address and outputting the word signal selecting an entry to the tag memory and the data memory in response to the entry index signal, the write control signal and a write way signal.

DETAILED DESCRIPTION It is, therefore, an object of the present invention to provide an address translation unit which carries out the address translation with variable page sizes at high speed, and which can be realized to minimum area.

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