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Apparatus and method for an improved content addressable memory using a random access memory to generate match information
| Details |
Inventors: Edgar, Ron;
Assignee: Digital Equipment Corporation (Maynard, MA)
Primary Examiner: Gossage; Glenn
Assistant Examiner: Kim; Matthew M.
Attorney, Agent or Firm: Kenyon & Kenyon
A content addressable memory, utilizing address recognition mechanism, comprising a Random Access Memory (RAM) including a plurality of data storage locations. Each of the data storage locations has a unique address. The content addressable memory operates to store a data entry comprising predetermined match information for at least a portion of a data entity. Each at least a portion of a data entity comprises the unique address of the respective data storage location. The RAM has an address port for input of at least a portion of a data entity as an address and an output for outputting the stored data entries. The RAM operates to fetch the data entry stored at the input address and to output the stored match information corresponding to the at least a portion of a data entity, in response to input of the at least a portion of a data entity as an address to the RAM. In a particular embodiment, the RAM comprises an array of n RAMs, wherein the at least a portion of a data entity is segmented into n slices. Each of the slices is used as an address to a respective one of said array of n RAMs. |
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DETAILED DESCRIPTION The present invention provides a fast, highly-reliable content addressable memory.
Generally, the present invention comprises a RAM memory, the contents of which is retrievable based upon the substance or meaning of the contents.
The RAM is arranged at initialization as a look-up table containing data entries which comprise match information indicating whether there is a match for an input data entity to be input as an address,to the RAM.
The data entry is fetched by addressing the data storage location containing the data entry.
The RAM will output the data entry which indicates correspondence between the input data entity and the content of the entry, i.
e.
, whether or not a match exists.
Thus, the information stored in the memory of the RAM is meaningfully associated with the input data entity used as an address to access the information contained therein.
In one particular implementation, a unique input data entity is used as an address for the RAM to access a unique one bit wide data storage location in the RAM containing a one bit wide data entry.
The state of each one bit data location is initialized as either a "1" or a "0" indicating whether or not a match exists for the input data entity used as the RAM address, i.
e.
, whether the input data entity is a data entity to be recognized within the sparsely populated matrix.
Thus, the RAM output will comprise match information indicating correspondence between the input data entity and the one bit wide data entry contained in the memory.
As the need for a wider input data entity arises, for example, a 48-bit wide input data entity, the RAM size required for use in accordance with the present invention becomes cumbersome or not physically feasible.
Thus, according to a feature of the present invention, when large data entities are to be recognized, a functional RAM of the content addressable memory may be effectively achieved using, for example, n relatively small RAMS connected in parallel.
In accordance with a feature of this implementation of the present invention, the input data entity is partitioned into n slices, each of the n slices representing an address to a particular one of the n smaller RAMs
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