 Digital programmable timing device |
| What is claimed is: 1. A system for synchronizing analog data from a rotating device having a ... |
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| Character information processing system |
| An object of the present invention is to provide a novel character recognition system. In the ... |
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| Musical tone waveshape generator |
| It is, therefore, an object of the invention to provide a novel musical tone waveshape generator ... |
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| Polyphonic computer organ |
| The musical instrument according to the invention is a truly polyphonic instrument which is not ... |
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| Electronic musical instrument |
| What is claimed is: 1. An electronic musical instrument comprising: a plurality of selectively ... |
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| Artificial random-number pattern generating circuit |
| It is, therefore, an object of the invention to overcome the problems existing in the conventional ... |
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| Data processing apparatus |
| According to the invention there is provided data processing apparatus comprising a plurality of ... |
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| Digital synthesis technique for pulses having predetermined time and frequency domain characteristics |
| In FIG. 1, an illustrative embodiment of the invention performs the digital synthesis technique to ... |
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Apparatus and method for enhancing data transfer to or from a SDRAM system
| Details |
Inventors: Reeves, Earl C.;
Assignee: Compaq Computer Corp. (Houston, TX)
Primary Examiner: Butler; Dennis M.
Assistant Examiner:
Attorney, Agent or Firm: Daffer; Kevin L. Conley, Rose & Tayon
A computer system, bus interface unit employing a memory controller, and method are presented for optimizing the bandwidth data, address, and control transfer rates across a memory bus coupled to an SDRAM system. The SDRAM system is partitioned such that one partition will undergo pre-charge or refresh in the interim between times in which another partition (or a pair of partitions) initiate a burst read. The burst read cycles coincide with an initial column address of the burst, and are spaced a number of cycles equal to the burst length. Proper spacing of the initial column address, or read request, relative to a non-read requested partition ensures data read from the activated partition will be placed on the memory data bus in seamless fashion. That is, there are no non-data transfers occurring between data burst cycles, even though refresh or pre-charge operations are performed on a non-read partition. Careful placement of the hidden refresh cycles encountered by one partition relative to read cycles on other partitions ensures the data flow resulting therefrom will be optimized to sustain peak bandwidth on a synchronous DRAM memory bus. |
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DETAILED DESCRIPTION The problems outlined above are in large part solved by an improved memory bus transfer technique hereof.
The present transfer technique is one which can perform three of more consecutive and unbroken fetches of cache line data from the memory to a requesting device.
The requesting device can be either the processor or a peripheral performing access through a DMA cycle.
The three consecutive fetches incur a data transfer that occupies no more than 12 system clock cycles, given a burst length of four cycles per burst.
The fetched data arise from partitions within the SDRAM system.
Those partitions may include a minimum of one SDRAM chip.
If an entire cache line is desired to be transferred within a single system clock cycle, then the partition being read includes a plurality of SDRAM chips commonly connected through a chip select signal.
The partitioned group of chips can be arranged on a separate printed circuit board, such as that attributed to a DIMM.
During the time in which one partition is being read (i.
e.
, data being transferred therefrom), another partition may undergo a refresh or pre-charge operation.
However, the refresh or pre-charge operations which occur within any given partition do not occur consecutively between read requests attributed to another partition or another pair of partitions.
In other words, the present transfer technique ensures the refresh and pre-fetch operations of one partition be separated in time by a read request attributed to another partition.
In the example in which three partitions are used, the present transfer technique purposely interposes a read request to a second partition between a pre-charge and refresh operations associated with a third partition.
In this fashion, a read request to a first partition can initiate data transfer of N burst cycles (where N is preferably four or more), followed immediately by data burst cycles attributed to the second partition read request, even though a pre-charge or refresh operation may occur on the third partition in the interim
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