Apparatus and method for reducing power consumption in a computer system

DETAILED DESCRIPTION A method and apparatus for reducing the power consumption of a processor in a computer system is described.
The present invention includes a programming structure running on the processor that determines when the processor is in an inactive state.
The programming means causes a signal to be generated if the processor is in the inactive state.
The signal is received by control logic that controls power and clocking signals to the processor.
The control logic in response to the signal from the programming means generates two signals, one to a phase-locked loop that clocks the processor and a second to a switch that connects the processor to the power supply.
The signals from the control logic disable the clock signals to the processor and then decouple the power supply to the processor when the processor is in the inactive state.
The clock signals from the PLL are disabled while maintaining synchronization.
In the present invention, the control logic also controls the switch and the PLL to couple the processor to the power supply and then enable the clock signals in response to a periodic interrupt signal, a non-periodic interrupt or a bus request from a peripheral device.
Thereafter, the programming structure signals the control logic again when it determines that the processor again reenters an inactive state, such that the control logic disables the clock signals and decouples the power supply to the processor until the next interrupt or bus request.
The present invention also offers an abort path to prevent processor power down in the event of a late arriving wake-up event (e.
g.
, interrupt), and offers a power-down method to support a system low power sleep mode where the contents of memory are preserved.