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Arithmetic-and-logic-unit-with-prior-state-dependent-logic-operations

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Arithmetic and logic unit with prior state dependent logic operations

Details

Inventors: Ando, Hideki; Machida, Hirohisa;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Malzahn; David H.
Assistant Examiner:
Attorney, Agent or Firm: Lowe, Price, Leblanc, Becker & Shur

The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of instruction steps. The arithmetic and logic unit of the present invention has a control portion provided with a control circuit for performing the specified operation such as operation of MAD by a small number of instruction steps.

DETAILED DESCRIPTION The present invention has been accomplished in view of such necessity and it is an object of the present invention to provide an arithmetic and logic unit in a microprocessor, in which hardware is improved to perform prescribed operation such as MAD operation with a small number of instruction steps.
An arithmetic and logic unit in accordance with the present invention comprises, in a control portion, a control circuit for performing prescribed operation such as MAD operation with a small number of instruction steps.
If the arithmetic and logic unit of the present invention is used, prescribed operation such as MAD operation, which would be performed with a relatively large number of instruction steps in a conventional microprocessor, can be performed with a very small number of instruction steps by means of a control circuit.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

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