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Semiconductor integrated circuit device |
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Barrel driving device for camera |
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Cellular automaton for generating random data |
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Explicit specification of valid compound document data stream structure and content |
| It is therefore an object of the present invention to provide a way to explicitly define the valid ... |
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Output buffer with ground bounce compensation |
| It is a general object of the present invention to provide a ground bounce compensating output ... |
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Routing address bit selection in a packet switching network |
| Turning now to the drawing, FIG. 1 is a representation of a packet switching network 100 of the ... |
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Optical distribution of analog and digital signals using optical modulators with complementary outputs |
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Apparatus and method for reconstructing data |
| OF THE PREFERRED EMBODIMENT FIG. 1 shows a schematic and block diagram of the exact embodiment of ... |
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Associative memory architecture
| Details |
Inventors: Ali-Yahia, Tahar; Dana, Michel;
Assignee: France Telecom-Etablissement Autonome De Droit Public (Paris, FR)
Primary Examiner: Swann; Tod R.
Assistant Examiner: Asta; Frank J.
Attorney, Agent or Firm: Pearne, Gordon, McCoy & Granger
An association memory which permits the execution of all kinds of comparative operations. The associative memory includes a memory map (1) in which a search argument, which has been processed in a scanning module (3) and a masking unit (5,7), is compared to the data stored in the memory. After this comparison, the data obtained is recorded in a response register (11). When the search data and the stored data supply an association of variable length words, the result data is processed in a module for the processing of variable-length words (13) and in a multiple-response management module. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a functional schematic drawing of the associative memory architecture covered by the present invention is provided. This associative memory includes different types of elements, namely storage elements, processing elements, and routing elements for data and addresses. The storage elements are made up of different registers, such as an address register, a data register, a response register and a masking register. The processing elements are made up of a masking unit, a scanning module, an associative memory map, a multiple response management module, a module for processing variable-length words and a control unit. In FIG. 1, the address bus is labeled AB and the data bus DB, these buses allowing for the routing of the addresses (Ad) and the data (Arg), respectively, in particular to the scanning module, memory map and control unit. The memory map (1) is made up of a set of static memory nodes, each node being generally constituted by a set of transistors and a comparison logic. In effect, the search arguments (Arg) input into the associative memory are compared with the data stored in memory (for example, in a data register). In addition to a memory map (1), the comparison media or means also include a scanning module (3), masking register (5) and masking unit (7). The associative memory also includes manipulation media or means made up of a storage module for results (9), a response register (11), a processing module for variable-length words (13) and a multiple response management module (15). In addition, it includes an address register (17) and a decoder (19). The control unit (21) ensures the control of information exchanges between the different modules and registers of the associative memory. The search argument (Arg) is input into the comparison media or means and, more specifically, into the scanning module (3), by means of the data bus (DB). Similarly, the data contained in the memory map (1) are also sent down the data bus (DB), and the control unit (21) receives and manages information about these data
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