Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home CPUs Asynchronous-PCM-common-decoding-apparatus

 Asynchronous PCM common decoding apparatus

Details
Inventors: Maruta, Rikio; Itoh, Yasuo; Tomozawa, Atsushi;
Assignee: Nippon Electric Co., Ltd. (Tokyo, JP)
Primary Examiner: Stewart; David L.
Assistant Examiner:
Attorney, Agent or Firm: Sughrue, Rothwell, Mion, Zinn and Macpeak

An asynchronous PCM common decoding apparatus decodes asynchronous PCM signals sent from a plurality of transmitter sources. The apparatus includes a plurality of receiver units each of which generate a digital signal to be decoded, a channel-number-designating signal, and a decode-requesting signal. One or more decoders are provided to decode the digital signals from the receiver units to analog signals. The decoders produce status signals indicating availabilities of the decoders for decoding the digital signals. A common control unit is responsive to both the decode-requesting signals and the status signals to successively allot a combination of a given receiver and a given decoder.

DETAILED DESCRIPTION It is one object of the present invention to provide an asynchronous PCM common decoding apparatus free from the above-mentioned disadvantages of the prior art systems and capable of making economical multidestinational operations possible.
Another object of the present invention is to provide an asynchronous PCM common decoding apparatus capable of receiving a plurality of digital signals asynchronous to each other and capable of decoding the received signals by means of a common decoder.
The present PCM common decoding apparatus in which a plurality of time division multiplexed digital signals asynchronous to each other are received and decoded, is comprised of a plurality of receiver units each of which generates at its output a digital signal to be decoded, a channel-number-designating signal for designating the number of the channel to which an analog signal obtained from the decoding of said digital signal is to be fed, and a decode-requesting signal for requesting the decoding of said digital signal, one or more decoders each of which produces at its output a status signal for representing that said digital signals given from said receiver unit are acceptable, and a common control unit responsive to said request signals given from said receiver units and said status signals given from said one or more decoders for successively allotting a combination of a given receiver and a given decoder and for sending a data transfer command signal to the allotted receiver unit so that said digital signal to be decoded and said channel-number designating signal for designating the number of the channel may be transferred from the allotted receiver unit to the allotted decoder and also sending a decode command signal to said decoder.



Related patents
  Mechanism for broadcasting data in a massively parallell array processing system
The invention provides a new and improved array processing system having a plurality of processing elements each with a processor and an associated memory. In still ...
  Reducing the number of carry-look-ahead adder stages in high-speed arithmetic units, structure and method
According to the invention, an add circuit for adding an addend and an augend and generating a final sum is described. The addend, augend, and final sum are binary ...
  Method for managing multiple versions of multiple subsystems in a distributed computing environment
The disclosed embodiment involves three parts: recording the software level information, reporting (retrieving) that level information, and uniform management of a ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved