DETAILED DESCRIPTION According to the invention, a digital circuit, sub-system or system includes one or more portions (i.
e.
, domains) that are independently clocked with separate, adjustable clocks.
Each clock is an asynchronous stop/start clock used in implementing a self-tuning clocking methodology.
Each domain includes a plurality of digital circuit building blocks (i.
e.
, register transfer modules--RTMs) which combine to perform a particular function or functions (e.
g.
, memory, adder, co-processor, processor, computer).
According to the self-tuning methodology, a maximum clocking rate of a domain is measured.
The clock, then, is adjusted to run at this rate, or more preferably, at nearly this rate.
The maximum clocking rate can only be as fast as the slowest circuit in the domain, including any latency for clock distribution within the domain.
At design time, the domain is analyzed to identify its slowest RTM.
The performance of such RTM then is measured during operation to determine a maximum clocking period.
As performance varies, the clock is adjusted (i.
e.
, tuned), so that the domain always runs at nearly maximum speed.
According to alternate embodiments, the time between detection of a change in circuit speed and adjustment of the clock may vary.
Because each domain is independently clocked, the respective domains operate asynchronously.
Thus, there is need for a reliable method of transferring data between domains.
According to the invention, the clock cycles of two domains are generally synchronized during an inter-domain data transfer.
According to one aspect of the invention, the adjustable clock is formed by a mutual exclusion element, an inverting gate and an adjustable delay line.
The three circuits form a self-inverting loop which defines a clock period.
The delay line receives a programmable input for adjusting the clock period.
The mutual exclusion element serves as an arbiter between the self-inverting loop clock pulse and a data request line.
When the clock pulse wins the arbitration, the clock cycle transitioning continues
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