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Home CPUs Automatic-A-D-converter-operation-with-selectable-result-format

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 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST*** *** NO IMAGES AVAILABLE***
Description:...


 Automatic A/D converter operation with selectable result format

Details
Inventors: Campbell, Jr., Jules D.; Shaw, Craig D.; Huston, William DeWitt;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Hoff; Marc S.
Assistant Examiner:
Attorney, Agent or Firm: Meyer; Jonathan P.

An analog-to-digital conversion system and method provide selectable data formats for each converted digital result value. Each digital result is stored in a register or table word. Information from a host processor is used to select a desired data format. In one embodiment the address range used to read the digital result serves to select the appropriate data format option, which may be, for example, left-justified or right-justified data, and signed or unsigned data. In another embodiment, one or more command words from the processor are used to select the desired data format.

DETAILED DESCRIPTION What is claimed is: 1.
An analog-to-digital conversion system comprising: (a) an address bus; (b) an N-bit data bus; (c) an analog input terminal; (d) a sample and hold circuit having an input coupled to the analog input terminal and having an output; (e) an analog-to-digital converter circuit having an input coupled to the output of the sample and hold circuit and having an M-bit digital output, where M is less than N; (f) an interface circuit coupled to receive an address from the address bus and coupled to provide data to the data bus, the interface circuit also having an input coupled to the M-bit digital output of the analog-to-digital converter, the interface circuit further comprises: a data format circuit coupled to receive at least a portion of the address, the data format circuit couples an M-bit digital signal received from the analog-to-digital converter to either a first portion of the N-bit data bus or a second portion of the N-bit data bus, depending on a value of the portion of the address received by the data format circuit.
2.
An analog-to-digital conversion system according to claim 1 wherein the data format circuit further comprises: means for coupling the M-bit digital output to a least significant M bits of the N-bit data bus; and means for coupling the M-bit digital output to a most significant M bits of the N-bit data bus.
3.
An analog-to-digital conversion system according to claim 2 wherein the data format circuit further comprises: means for coupling the M-bit digital output to a most significant M bits of the N-bit data bus and for inverting a most significant bit of the M-bit digital output.
4.
An analog-to-digital conversion system according to claim 2 wherein the data format circuit further comprises: means for coupling the M-bit digital output to a least significant M bits of the N-bit data bus and for coupling a most significant bit of the M-bit digital output to each of the N minus M most significant bits of the N-bit data bus.
5.
An analog-to-digital conversion system according to claim 2 wherein the data format circuit further comprises: means for coupling the M-bit digital output to a least significant M bits of the N-bit data bus and for coupling a most significant bit of the M-bit digital output to a most significant bit of the N-bit data bus



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