Branch control circuit

DETAILED DESCRIPTION To solve these problems, an object of the present invention is to provide a branch control circuit that can minimize confusion in the pipeline due to a branch instruction, without increasing the hardware.
In order to accomplish the object, the present invention provides a branch prediction control circuit comprising a first register for holding at least one machine language instruction fetched from a memory; a second register for holding an address of the machine language instruction; a first detection circuit connected to the first register to detect that the first register contains a relative branch instruction which is predicted to be taken, and provide a branch address valid signal; and an adder for adding a displacement included in the relative branch instruction to the address held in the second register and providing a branch target address.
According to a branch control circuit of the present invention, a sub-decoding circuit is arranged outside a main decoding circuit.
The sub-decoding circuit handles only a short format relative branch instruction that frequently appears, to predict whether or not the branch instruction is taken.
A branch address is found by adding the address of the relative branch instruction to a displacement contained in the branch instruction.
This branch control circuit of the present invention can be formed with small hardware.
Since the present invention does not require branch addresses to be stored, the memory for storing the branch addresses can be omitted, and confusion caused by successful branching in a pipeline can be minimized.
These and other objects, features and advantages of the present invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings.