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Bus-adapter-module-with-improved-error-recovery-in-a-multibus-computer-system

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Bus adapter module with improved error recovery in a multibus computer system

Details

Inventors: Hartwell, David W.; Bloom, Elbert; Triolo, Victoria M.;
Assignee: Digital Equipment Corporation (Maynard, MA)
Primary Examiner: Pellinen; A. D.
Assistant Examiner: Evans; Geoffrey S.
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner

A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.

DETAILED DESCRIPTION It is an object of the present invention to provide a method and apparatus for error recovery in a multibus computer system that maintains system integrity while providing higher system reliability than in prior art systems.
Another object of the invention is to provide a method and apparatus for recovering from errors occurring during inter-bus READ transactions in a multibus computer system which will not result in a system shut-down yet which will produce a system shut-down if such errors occur during inter-bus WRITE transactions.
It is yet another object of the invention to provide a method and apparatus for repeating a READ transaction when an error occurs during an inter-bus READ transaction.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description or may be learned by practice of the invention.
The objects and advantages of the invention will be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention maintains system integrity by causing a system shut-down when non-recoverable errors occur during WRITE transactions but reduces unnecessary system shut-downs caused by recoverable errors during READ transactions by initiating a repeat of the READ transaction instead of a system shut-down when an error occurs during a READ transaction.
The invention provides a control adapter module providing error recovery in a computer system including a first bus, connected to an interconnect bus through a response adapter module, and a second bus, the second bus having a plurality of data lines and a plurality of command lines carrying command signals to initiate execution of a plurality of types of transactions on the second bus, the response module including a logic circuit asserting a RECOVERABLE ERROR signal when a parity error occurs during a READ transaction and asserting a NON-RECOVERABLE ERROR signal when a parity error occurs during a WRITE transaction to initiate a system shut-down

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