Home | Links | Contact Us | More About Intellectual Property | Bookmark

Search patents:

Home

CPUs

Bus-control-method-and-apparatus

Coordinate input system and input implement used in the system

Accordingly, an object of the present invention is to provide a coordinate input system which does ...

Integrated circuit board system and an integrated circuit board assembly for application thereto

Accordingly, an object of the present invention is to provide a wide variety of system control ...

Variable length backplane bus

The present invention solves these and other problems by providing a backplane bus that can serve a ...

Method for reclaiming unused system resources

This need and others are substantially met by the method for reclaiming unused system resources ...

Electro-optical header connector

The object of this invention is to provide an improved header connector for a connection system ...

Installation of an optical component in an optical device

What is claimed is: 1. An installation structure of an optical component for use in an optical ...

Switching element and method for controlling the same

The object of the invention is to introduce a new switching element and method for controlling the ...

Electrical contact and connector

It is therefore a primary object of the present invention to enhance the electrical contact art. It ...

Zero-insertion force electrical connector

OF THE INVENTION A preferred embodiment of the connector 20 of this invention includes the female ...

Reduced insertion force connector

It is one of the objects of the present invention to provide a simplified way of manufacturing low ...

Bus control method and apparatus

Details

Inventors: Yabushita, Masaharu; Nohmi, Makoto; Fujikura, Nobuyuki; Miyamoto, Shoji; Ihara, Hirokazu;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Eng; David Y.
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry & Wands

A bus control method and apparatus wherein buses each coupling a pair of processors are serially arranged rectilinearly into a cluster bus which is arranged in one direction and wherein a plurality of such cluster buses are arranged in a plurality of directions as a lattice pattern to form a multiprocessor system. Each of the processors supplies the respective cluster buses with send request and priority processing level signals and receives a receipt acknowledge signal from another processor on the same cluster bus, thereby to occupy said cluster bus, so as to transfer data to the other processor on the cluster bus.

DETAILED DESCRIPTION An object of the present invention is to provide a bus control method and apparatus which, in order to eliminate these disadvantages of the prior art, dispenses with a bus arbiter for controlling the commpon bus of a multiprocessor system, thereby to secure a high reliability and provide for maintainability of the system.
The present invention is characterized in that a plurality of buses, each of which couples a pair of processors, are serially arranged rectilinearly into one cluster bus, such cluster bus or buses being arrayed in one direction or in a plurality of directions as a lattice pattern when viewed in plan, so as to form a multiprocessor system, and that each processor delivers a send request and a priority processing level signal to every corresponding cluster bus and receives a receipt acknowledge signal from another processor belonging to the same cluster bus, thereby to occupy the cluster bus and to transfer data to the other processor of the cluster bus.
The invention is also characterized in that each of the processors is connected to the cluster bus through a bus control device which consists of I/O ports and a relay bus control unit.

Related patents

	Method of automatically extracting a contrasting object in a digital image What is claimed is: 1. A method for extracting a contrasting object in a digital image comprising: estimating for each picture element (i,j) a threshold S.sub.1 ...
	Computer memory apparatus The above and other objects are achieved in a preferred embodiment of the memory subsystem of the present invention which couples to a bus in common with a central ...
	Electro-optic binary adder What is claimed is: 1. An electro-optic adder for summing binary addends having N bits comprising: an electrically non-conductive substrate; N + 1 optical waveguides ...
	Resolution conversion of bitmap images using error term averaging OF AN ILLUSTRATIVE EMBODIMENT In FIG. 1, an image conversion system is shown having an image converter 10 for converting an image in an input bitmap 12 to an image in ...
	*WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST* * NO IMAGES AVAILABLE* Description:...
	Concentrator system with polling-response means for detecting failures to stop tariff charges on locally established intraoffice calls It is therefore an object of the present invention to discontinue the operation of the tariff counter of a calling party setting up a local call in the event that the ...
	Method for testing a transceiver, and base station of a time-divisional radicommunication system FIG. 1 shows part of a preferred embodiment of the base station according to the invention. FIG. 1 illustrates a transceiver unit 1 of a base station in the GSM system. ...
	N+K sparing in a telecommunications switching environment FIGS. 1 and 2 show in block diagram form an illustrative switching system of a self-routing telecommunications system. The switching system comprises a switching ...
	Heatsink package for flip-chip IC Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a method of producing the semiconductor device, in ...
	Color television transmission or information storage system, respectively with time-division multiplex coding and data generator and receiver suitable therefor The invention has for its object to provide a color television transmission or information storage system, respectively using time-division multiplex coding, in which ...

0.054
Archive: All patents - Links Copyright (c)2006 Eipa-patents.org - All rights reserved