|
|
Intermediate output buffer circuit for semiconductor memory device
In accordance with an embodiment of the invention, an MOS RAM using one-transistor cells employs a bistable sense amplifier in the center of each column line. An ...
|
|
|
Means and method for controlling eluent gradient in liquid chromatography
Briefly stated, according to one aspect of the invention the foregoing objects are achieved by providing a substantially linear, increasing signal extending between ...
|
|
|
Transistor differential amplifier circuit
Accordingly, one of the objects of the present invention is to provide an improved transistor differential amplifier circuit which is able to produce output pulse ...
|
|
|
Data processing system having centralized bus priority resolution
In accordance with this invention a bus allocator, connected to one or more common buses to which one or more units capable of regulating allocation of the common buses, ...
|
|
|
Data processor with improved loop handling utilizing improved register allocation
It is an object of the present invention to provide a data processing method and data processor capable of accessing registers greater in number than registers ...
|
|
|
Circuitry and method for performing two operating instructions during a single clock in a processing device
Briefly, in one embodiment, the present invention comprises method for performing two operating instructions during a single clock cycle in a processing device the ...
|
|
|
Verification of instruction and data fetch resources in a functional model of a speculative out-of order computer system
OF THE PRESENT INVENTION 1. Description The preferred embodiment of the present invention is discussed below with reference to the drawings, where like reference ...
|
|
|
Data processor
An object of the present invention is to provide a high-performance processor capable of executing software using a new architecture (instruction system) while ...
|
|
|
Multiprocessor system with cascaded modules combining processors through a programmable logic cell array
Accordingly, there is provided a multiprocessor data processing system embodying the invention including a plurality of cascaded modules. Each of the cascaded modules ...
|
|
|
System and method for processing external conditional branch instructions
An object of this invention is to execute a conditional branch instruction where the condition to be evaluated is obtained from a designator resident on a VLSI gate ...
|